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參數(shù)資料
| 型號： | CY7C09379-6AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 32K/64K X 16/18 Synchronous Dual Port Static RAM |
| 中文描述： | 32K X 18 DUAL-PORT SRAM, 15 ns, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 342K |
| 代理商： | CY7C09379-6AC |
CY7C09279/89
CY7C09379/89
Document #: 38-06040 Rev. **
Page 4 of 18
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature.................................
–
65
°
C to +150
°
C
Ambient Temperature with Power Applied..
–
55
°
C to +125
°
C
Supply Voltage to Ground Potential...............
–
0.3V to +7.0V
DC Voltage Applied to
Outputs in High Z State .................................
–
0.5V to +7.0V
DC Input Voltage............................................
–
0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >1100V
Latch-Up Current.....................................................>200 mA
Pin Definitions
Left Port
A
0L
–
A
15L
ADS
L
Right Port
A
0R
–
A
15R
ADS
R
Description
Address Inputs (A
0
–
A
14
for 32K, A
0
–
A
15
for 64K devices).
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
Chip Enable Input. To select either the left or right port, both CE
0
AND CE
1
must be asserted
to their active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respec-
tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
0
–
I/O
15
for x16 devices).
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte. (I/O
0
–
I/O
8
for x18, I/O
0
–
I/O
7
for x16) of the memory array. For read operations both
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O
8/9L
–
I/O
15/17L
).
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
CE
0L
,CE
1L
CE
0R
,CE
1R
CLK
L
CNTEN
L
CLK
R
CNTEN
R
CNTRST
L
CNTRST
R
I/O
0L
–
I/O
17L
LB
L
I/O
0R
–
I/O
17R
LB
R
UB
L
OE
L
UB
R
OE
R
R/W
L
R/W
R
FT/PIPE
L
FT/PIPE
R
GND
NC
V
CC
Operating Range
Range
Ambient
Temperature
0
°
C to +70
°
C
–
40
°
C to +85
°
C
V
CC
Commercial
Industrial
[9]
5V
±
10%
5V
±
10%
Note:
9.
Industrial parts are available in CY7C09289 and Cy7C09389 only
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