參數(shù)資料
型號(hào): CY7C09379-6AC
廠(chǎng)商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: 32K/64K X 16/18 Synchronous Dual Port Static RAM
中文描述: 32K X 18 DUAL-PORT SRAM, 15 ns, PQFP100
封裝: PLASTIC, TQFP-100
文件頁(yè)數(shù): 2/18頁(yè)
文件大?。?/td> 342K
代理商: CY7C09379-6AC
CY7C09279/89
CY7C09379/89
Document #: 38-06040 Rev. **
Page 2 of 18
Functional Description
The CY7C09279/89 and CY7C09379/89 are high-speed syn-
chronous CMOS 32K, and 64K x 16/18 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.
[5]
Reg-
isters on control, address, and data lines allow for minimal set-
up and hold times. In pipelined output mode, data is registered
for decreased cycle time. Clock to data valid t
CD2
= 6.5 ns
[1]
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available
t
CD1
= 15 ns
after the
address is clocked into the device. Pipelined output or flow-
through mode is selected via the FT/PIPE pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW-
to-HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE
0
or LOW on CE
1
for one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE
0
LOW and CE
1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port
s burst counter is loaded with the port
s Address Strobe
(ADS). When the port
s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port
s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Pin Configurations
Notes:
5.
6.
7.
When writing simultaneously to the same location, the final value cannot be guaranteed.
This pin is NC for CY7C09279.
For CY7C09279, pin #18 connected to V
CC
is equivalent to an IDT x16 pipelined device; connecting pin #18 and #58 to GND is equivalent to an IDT x16 flow-
through device.
1
2
3
92 91 90
84
85
87 86
88
89
83 82 81
76
78 77
79
80
93
94
95
96
97
98
99
100
59
60
61
67
66
64
65
63
62
68
69
70
75
74
73
72
71
A9R
A10R
A11R
A12R
A13R
A14R
UBR
NC
LBR
CE1R
CNTRSTR
OER
FT/PIPER
NC
A15R
GND
R/WR
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
CE0R
58
57
56
55
54
53
52
51
A9L
A10L
A11L
A12L
A13L
A14L
UBL
NC
LBL
CE1L
CNTRSTL
OEL
FT/PIPEL
GND
NC
A15L
VCC
R/WL
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
CE0L
17
18
19
16
15
9
10
12
11
13
14
8
7
6
4
5
20
21
22
23
24
25
A
A
A
A
A
A
C
A
C
G
A
A
A
A
A
C
C
A
A
A
A
A
A
A
A
34 35 36
42
41
39 40
38
37
43 44 45
50
48 49
47
46
N
I
I
I
V
I
I
I
I
G
I
I
I
I
I
I
G
I
I
I
I
V
I
I
I
33
32
31
30
29
28
27
26
100-Pin TQFP (Top View)
[6]
[6]
[7]
[7]
CY7C09279 (32K x 16)
CY7C09289 (64K x 16)
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