參數(shù)資料
型號: CY7C09199V
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 128K x 9 Synchronous Dual-Port Static RAM(3.3V 128K x 9 同步雙端口靜態(tài)RAM)
中文描述: 3.3 128K的× 9同步雙端口靜態(tài)RAM(3.3 128K的× 9同步雙端口靜態(tài)RAM)的
文件頁數(shù): 15/18頁
文件大?。?/td> 580K
代理商: CY7C09199V
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *B
Page 15 of 18
Notes:
34.“X” = “Don’t Care”, “H” = V
, “L” = V
.
35.ADS, CNTEN, CNTRST = “Don’t Care.”
36.OE is an asynchronous input signal.
37.When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
38.CE
and OE = V
; CE
and R/W = V
.
39.Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
40.Counter operation is independent of CE
0
and CE
1
.
Read/Write and Enable Operation
[34, 35, 36]
Inputs
Outputs
OE
CLK
CE
0
H
CE
1
X
R/W
I/O
0
I/O
9
Operation
X
X
High-Z
Deselected
[37]
X
X
L
X
High-Z
Deselected
[37]
X
L
H
L
D
IN
Write
L
L
H
H
D
OUT
Read
[37]
H
X
L
H
X
High-Z
Outputs Disabled
Address Counter Control Operation
[34, 38, 39, 40]
Address
X
Previous
Address
X
CLK
ADS
X
CNTEN
X
CNTRST
L
I/O
Mode
Reset
Operation
D
out(0)
Counter Reset to Address 0
A
n
X
L
X
H
D
out(n)
Load
Address Load into Counter
X
A
n
H
H
H
D
out(n)
Hold
External Address Blocked—Counter
Disabled
Counter Enabled—Internal Address
Generation
X
A
n
H
L
H
D
out(n+1)
Increment
相關(guān)PDF資料
PDF描述
CY7C09179 32K x 9 Synchronous Dual-Port Static RAM(32K x 9 同步雙端口靜態(tài)RAM)
CY7C09079 32K x 8 Synchronous Dual-Port Static RAM(32K x 8 同步雙端口靜態(tài)RAM)
CY7C09089 64K x 8 Synchronous Dual-Port Static RAM(64K x 8 同步雙端口靜態(tài)RAM)
CY7C09099 128K x 8 Synchronous Dual-Port Static RAM(128K x 8 同步雙端口靜態(tài)RAM)
CY7C09189 64K x 9 Synchronous Dual-Port Static RAM(64K x 9 同步雙端口靜態(tài)RAM)
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