參數(shù)資料
型號(hào)： CY7C0832V-167AXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 256K X 18 DUAL-PORT SRAM, 4 ns, PQFP120
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120
文件頁(yè)數(shù)： 30/32頁(yè)
文件大?。?/td> 895K
代理商： CY7C0832V-167AXC
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I
Page 7 of 32
Master Reset
The CY7C0831V undergoes a complete reset by taking its
MRST input LOW. The MRST input can switch asynchro-
nously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox
Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. MRST must be performed on the CY7C0831V after
power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports. The highest
memory location, 1FFFF is the mailbox for the right port and
1FFFE is the mailbox for the left port. Table 2 shows that in
order to set the INTR flag, a Write operation by the left port to
address 1FFFF will assert INTR LOW. At least one byte has to
be active for a Write to generate an interrupt. A valid Read of
the 1FFFF location by the right port will reset INTR HIGH. At
least one byte has to be active in order for a Read to reset the
interrupt. When one port Writes to the other port’s mailbox, the
INT of the port that the mailbox belongs to is asserted LOW.
The INT is reset when the owner (port) of the mailbox Reads
the contents of the mailbox. The interrupt flag is set in
a flow-thru mode (i.e., it follows the clock edge of the writing
port). Also, the flag is reset in a flow-thru mode (i.e., it follows
the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Table 1. Address Counter and Counter-Mask Register Control Operation (Any Port)[ 4, 5]
CLK
MRST CNT/MSK
CNTRST
ADS
CNTEN
Operation
Description
X
L
X
Master Reset
Reset address counter to all 0s and mask
register to all 1s.
H
L
X
Counter Reset
Reset counter unmasked portion to all 0s.
H
L
Counter Load
Load counter with external address value
presented on address lines.
H
L
H
Counter Readback Read out counter internal value on
address lines.
H
L
Counter Increment Internally increment address counter
value.
H
Counter Hold
Constantly hold the address value for
multiple clock cycles.
H
L
X
Mask Reset
Reset mask register to all 1s.
H
L
H
L
Mask Load
Load mask register with value presented
on the address lines.
H
L
H
L
H
Mask Readback
Read out mask register value on address
lines.
H
L
H
X
Reserved
Operation undefined
Table 2. Interrupt Operation Example [1, 6, 7, 8]
Function
Left Port
Right Port
R/WL
CEL
A0L–16L
INTL
R/WR
CER
A0R–16R
INTR
Set Right INTR Flag
L
1FFFF
X
L
Reset Right INTR Flag
X
XXX
H
L
1FFFF
H
Set Left INTL Flag
X
L
1FFFE
X
Reset Left INTL Flag
H
L
1FFFE
H
X
Notes:
4.
“X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
5.
Counter operation and mask register operation is independent of chip enables.
6.
CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the
CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
7.
OE is “Don’t Care” for mailbox operation.
8.
At least one of B0, B1, B2, or B3 must be LOW.
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