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參數(shù)資料
| 型號： | CY7C0832V-167AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 DUAL-PORT SRAM, 4 ns, PQFP120 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120 |
| 文件頁數(shù)： | 10/32頁 |
| 文件大?。?/td> | 895K |
| 代理商： | CY7C0832V-167AXC |
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CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I
Page 18 of 32
tOHZ[19, 20]
OE to High Z
0
4.0
0
4.4
ns
tCD2
Clock to Data Valid
4.0
4.4
ns
tCA2
Clock to Counter Address Valid
4.0
4.4
ns
tCM2
Clock to Mask Register Readback Valid
4.0
4.4
ns
tDC
Data Output Hold After Clock HIGH
1.0
ns
tCKHZ[19, 20]
Clock HIGH to Output High Z
0
4.0
0
4.4
ns
tCKLZ[19, 20]
Clock HIGH to Output Low Z
1.0
4.0
1.0
4.4
ns
tSINT
Clock to INT Set Time
0.5
6.7
0.5
7.5
ns
tRINT
Clock to INT Reset Time
0.5
6.7
0.5
7.5
ns
tSCINT
Clock to CNTINT Set Time
0.5
5.0
0.5
5.7
ns
tRCINT
Clock to CNTINT Reset time
0.5
5.0
0.5
5.7
ns
Port to Port Delays
tCCS
Clock to Clock Skew
5.2
6.0
ns
Master Reset Timing
tRS
Master Reset Pulse Width
7.0
7.5
ns
tRSS
Master Reset Set-up Time
6.0
ns
tRSR
Master Reset Recovery Time
6.0
7.5
ns
tRSF
Master Reset to Outputs Inactive
6.0
6.5
ns
tRSCNTINT
Master Reset to Counter Interrupt Flag Reset Time
5.8
7.0
ns
JTAG Timing
Parameter
Description
CY7C0851V/CY7C0852V
Unit
-167/-133
Min.
Max.
fJTAG
Maximum JTAG TAP Controller Frequency
10
MHz
tTCYC
TCK Clock Cycle Time
100
ns
tTH
TCK Clock HIGH Time
40
ns
tTL
TCK Clock LOW Time
40
ns
tTMSS
TMS Set-up to TCK Clock Rise
10
ns
tTMSH
TMS Hold After TCK Clock Rise
10
ns
tTDIS
TDI Set-up to TCK Clock Rise
10
ns
tTDIH
TDI Hold After TCK Clock Rise
10
ns
tTDOV
TCK Clock LOW to TDO Valid
30
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
ns
Notes:
18. Except JTAG signals (tr and tf < 10 ns [max.]).
19. This parameter is guaranteed by design, but it is not production tested.
20. Test conditions used are Load 2.
Switching Characteristics Over the Operating Range (continued)
Parameter
Description
-167
-133
Unit
Min.
Max.
Min.
Max.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C0851AV-133AXC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0851AV-133BBC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0851AV-167AXC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0851AV-167BBC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0852AV-133BBC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C0832V-167BBC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 256KX18 4NS 144FBGA - Bulk |
| CY7C0833AV-100BBC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 9M-Bit 512K x 18 144-Pin FBGA |
| CY7C0833AV-133BBC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 9M-Bit 512K x 18 4.7ns 144-Pin FBGA 制造商:Rochester Electronics LLC 功能描述: |
| CY7C0833AV-133BBI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C0833V-100BBC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 9MBIT 512KX18 5NS 144FBGA - Bulk |
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