參數(shù)資料
型號: CY7B9950ACT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: 2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
中文描述: 7B SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32
文件頁數(shù): 3/9頁
文件大?。?/td> 168K
代理商: CY7B9950ACT
RoboClock
CY7B9950
Document #: 38-07338 Rev. *B
Page 3 of 9
Table 4. MF Calculation
In addition to determining whether the outputs synchronize to
the rising or the falling edge of the reference signal, the 3-level
PE/HD pin controls the output buffer drive strength as
indicated in
Table 6
.
The CY7B9950 features split power supply buses for Banks 1
and 2, Bank 3 and Bank 4, which enables the user to obtain
both 3.3V and 2.5V output signals from one device. The core
power supply (VDD) must be set a level that is equal or higher
than on any one of the output power supplies.
Governing Agencies
The following agencies provide specifications that apply to the
CY7B9950. The agency name and relevant specification is
listed below.
Notes:
5.
6.
7.
8.
LL disables outputs if TEST = MID and sOE# = HIGH.
When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID, sOE# disables them LOW when PE/HD = LOW.
Please refer to
DC Parameters
section for I
/I
specifications.
V
must not be set at a level higher than that of V
DD
. They can be set at different levels from each other, e.g., V
DD
= 3.3V, V
DDQ1
= 3.3V, V
DDQ3
= 2.5V
and V
DDQ4
= 2.5V.
FS
L
M
H
MF
32
16
8
f
NOM
at which t
U
is 1.0 ns(MHz)
31.25
62.5
125
Table 5. Output Skew Settings
nF[1:0]
LL
[5]
LM
LH
ML
MM
MH
HL
HM
HH
Skew (1Q[0:1],2Q[0:1])
4t
U
3t
U
2t
U
1t
U
Zero Skew
+1t
U
+2t
U
+3t
U
+4t
U
Skew (3Q[0:1])
Divide By 2
6t
U
4t
U
2t
U
Zero Skew
+2t
U
+4t
U
+6t
U
Divide By 4
Skew (4Q[0:1])
Divide By 2
v6t
U
4t
U
v2t
U
Zero Skew
+2t
U
+4t
U
+6t
U
Inverted
[6]
Table 6. PE/HD Settings
PE/HD
L
M
H
Synchronization
Negative
Positive
Positive
Output Drive Strength
[7]
Low Drive
High Drive
Low Drive
Table 7. Power Supply Constraints
V
DDQ1
[8]
3.3V
3.3V or 2.5V
2.5V
2.5V
V
DD
V
DDQ3
[8]
3.3V or 2.5V
2.5V
V
DDQ4
[8]
3.3V or 2.5V
2.5V
Table 8.
Agency Name
JEDEC
Specification
JESD 51 (Theta JA)
JESD 65 (Skew, Jitter)
1596.3 (Jitter Specs)
94 (Moisture Grading)
883E Method 1012.1 (Therma Theta JC)
IEEE
UL-194_V0
MIL
相關PDF資料
PDF描述
CY7B9950AI 2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7B9950AIT Precision, High-Side Current-Sense Amplifiers
CY7B9950AC 2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
CY7C0830AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
CY7C0831AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
相關代理商/技術參數(shù)
參數(shù)描述
CY7B9950AI 制造商:Rochester Electronics LLC 功能描述:2.5V/3.3V 200 MHZ PROGRAMMABLE SKEW CLOCK BUFFER IND TEMP - Bulk
CY7B9950AIT 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 32-Pin TQFP T/R
CY7B9950AXC 功能描述:鎖相環(huán) - PLL 2.5V/3.3V 200MHz COM Program Skw Clk Bufr RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
CY7B9950AXCT 功能描述:鎖相環(huán) - PLL 2.5V/3.3V 200MHz COM Program Skw Clk Bufr RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
CY7B9950AXI 功能描述:鎖相環(huán) - PLL 2.5/3.3V 200MHz HiSd PLL Clock Buffer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray