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參數(shù)資料
| 型號： | CY7B9950ACT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer |
| 中文描述： | 7B SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 168K |
| 代理商： | CY7B9950ACT |
2.5/3.3V, 200-MHz High-Speed Multi-Phase
PLL Clock Buffer
RoboClock
CY7B9950
Cypress Semiconductor Corporation
Document #: 38-07338 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised March 4, 2003
Features
2.5V or 3.3V operation
Split output bank power supplies
Output frequency range: 6 MHz to 200 MHz
Output-output skew < 100 ps
Cycle-cycle jitter < 100 ps
± 2% max output duty cycle
Selectable output drive strength
Selectable positive or negative edge synchronization
Eight LVTTL outputs driving 50
terminated lines
LVCMOS/LVTTL over-voltage-tolerant reference input
Phase adjustments in 625-/1250-ps steps up to +7.5 ns
2x, 4x multiply and (1/2)x, (1/4)x divide ratios
Spread-Spectrum-compatible
Industrial temp. range:
–
40
°
C to +85
°
C
32-pin TQFP package
Description
The CY7B9950 RoboClock
is a low-voltage, low-power,
eight-output, 200-MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high-performance computer and communication systems.
The user can program the phase of the output banks through
nF[0:1] pins. The adjustable phase feature allows the user to
skew the outputs to lead or lag the reference clock. Any one
of the outputs can be connected to feedback input to achieve
different reference frequency multiplication and divide ratios
and zero input-output delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the three-level PE/HD pin
controls the synchronization of the output signals to either the
rising or the falling edge of the reference clock and selects the
drive strength of the output buffers. The high drive option
(PE/HD = MID) increases the output current from ± 12 mA to
± 24 mA(3.3V).
Block Diagram
Pin Configuration
PE/HD
TEST
FS
3
3
REF
FB
2F1:0
1F1:0
3F1:0
4F1:0
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
4Q0
4Q1
PLL
3
3
3
3
3
3
3
3
Phase
Select
Phase
Select
Phase
Select
and /K
Phase
Select
and /M
3
sOE#
VDDQ1
VDDQ4
VDDQ3
1Q0
1Q1
VSS
VSS
3
F
V
R
V
T
2
2
CY7B9950
1
2
3
4
5
6
7
8
3F1
4F0
4F1
4Q0
VSS
4Q1
V
3
3
V
2
F
V
2
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
1F0
sOE#
VDDQ1
PE/HD
VDDQ4
1F1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B9950AI | 制造商:Rochester Electronics LLC 功能描述:2.5V/3.3V 200 MHZ PROGRAMMABLE SKEW CLOCK BUFFER IND TEMP - Bulk |
| CY7B9950AIT | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 32-Pin TQFP T/R |
| CY7B9950AXC | 功能描述:鎖相環(huán) - PLL 2.5V/3.3V 200MHz COM Program Skw Clk Bufr RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B9950AXCT | 功能描述:鎖相環(huán) - PLL 2.5V/3.3V 200MHz COM Program Skw Clk Bufr RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B9950AXI | 功能描述:鎖相環(huán) - PLL 2.5/3.3V 200MHz HiSd PLL Clock Buffer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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