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參數(shù)資料
| 型號(hào)： | CY7B9331 |
| 廠(chǎng)商： | Cypress Semiconductor Corp. |
| 英文描述： | HOTLink OLC Receiver(熱連接OLC接收器) |
| 中文描述： | 法律顧問(wèn)室的HOTLink接收器（熱連接法律顧問(wèn)室接收器） |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大小： | 112K |
| 代理商： | CY7B9331 |
CY7B9331
PRELIMINARY
2
CY7B9331 HOTLink Receiver Pin Description
Name
Q
0
7
(Q
b
h
)
SC/D(Q
a
)
I/O
TTL Out
Description
Q
0-7
Parallel Data Output. Q
0-7
contain the most recently received data. These outputs change syn-
chronously with Clk0. When MODE is HIGH, Q
0, 1, ...7
become Q
b, c,...h
respectively.
Special Character/Data Select. SC/D indicates the context of received data. HIGH indicates a Control
(Special Character) code, LOW indicates a Data character. When MODE is HIGH, SC/D acts as Q
a
output.
Received Violation Symbol. A HIGH on RVS indicates that a code rule violation has been detected in
the received data stream. A LOW shows that no error has been detected. In BIST mode, a LOW on
RVS indicates correct operation of the transmitter, receiver, and link on a byte-by-byte basis. When
MODE is HIGH, RVS acts as Q
j
output.
In Encoded mode, SYNC asserted HIGH indicates that new data has been received and is ready to
be delivered. SYNC asserted LOW shows that the received data is the Null character (normally
inserted by the transmitter as a pad between data inputs). In Bypass mode, SYNC stays LOW except
to indicate a K28.5 character when the framer is enabled (ENSYNC HIGH). In BIST mode, SYNC will
remain HIGH for all but the last byte of a test loop and will pulse LOW one byte time per BIST loop.
Recovered Byte Clock. This byte rate clock output is phase and frequency aligned to the incoming
serial data stream. SYNC, Q
0-7
, SC/D, and RVS all switch synchronously with the rising edge of this
output.
Serial Data Input Select. This ECL 100K (+5V referenced) input selects INB or INA as the active data
input. If LOOP is HIGH, INB is connected to the shifter and signals connected to INB will be decoded.
If LOOP is LOW INA is selected.
Serial Data Input A. The differential signal at the receiver end of the communication link may be
connected to the differential input pairs INA
±
or INB
±
. Either the INA pair or the INB pair can be used
as the main data input and the other can be used as a loopback channel or as an alternative data
input selected by the state of LOOP.
Serial Data Input B. This pin is either a single-ended ECL data receiver (INB) or half of the INB of the
differential pair. If STATUS is wired to V
CC
, then INB
±
can be used as differential line receiver inter-
changeably with INA
±
. If STATUS is normally connected and loaded, INB becomes a single-ended
ECL 100K (+5V referenced) serial data input. INB is used as the test clock while in Test mode.
Status Input. This pin is either a single-ended ECL status monitor input (SI) or half of the INB of the
differential pair. If STATUS is wired to V
CC
, then INB
±
can be used as differential line receiver inter-
changeably with INA
±
. If STATUS is normally connected and loaded, SI becomes a single-ended ECL
100K (+5V referenced) status monitor input.
Status Out. Status is the inverted TTL-translated output of SI. It is typically used to translate the Carrier
Detect output from a fiberoptic receiver. When this pin is normally connected and loaded (without any
external pull-up resistor), STATUS will assume the negative logical level of SI and INB will become a
single-ended ECL serial data input. If the status monitor translation is not desired, then STATUS may
be wired to V
CC
and the INB
±
pair may be used as a differential serial data input.
Reframe Enable. ENSYNC controls the Framer logic in the receiver. When ENSYNC is held HIGH,
each SYNC (K28.5) symbol detected in the shifter will frame the data that follows. When ENSYNC is
held LOW, the reframing logic is disabled. The incoming data stream is then continuously deserialized
and decoded using byte boundaries set by the internal byte counter. Bit errors in the data stream will
not cause alias SYNC characters to reframe the data erroneously.
Reference Clock. REFCLK is the clock frequency reference for the clock/data synchronizing PLL.
REFCLK sets the approximate center frequency for the internal PLL to track the incoming bit stream.
REFCLK must be connected to a crystal-controlled time base that runs within the frequency limits of
the Tx/Rx pair, and the frequency must be the same as the transmitter CKW frequency (within
CKW
±
0.1%).
Decoder Mode Select. The level on the MODE pin determines the decoding method to be used. When
wired to GND (Encoded Mode), MODE selects 8B/10B decoding. When wired to V
CC
(Bypass MODE),
registered shifter contents bypass the decoder and are sent to Q
a-j
directly. When left floating (internal
resistors hold the MODE pin at V
CC
/2) the internal bit clock generator is disabled and INB becomes
the bit rate test clock to be used for factory test. In typical applications, MODE is wired to V
CC
or GND.
TTL Out
RVS (Q
j
)
TTL Out
SYNC
TTL Out
CLK0
TTL Out
LOOP
ECL in
INA
±
Diff In
INB
(INB+)
ECL in
(Diff In )
SI
(INB
)
ECL in
(Diff In)
STATUS
TTL Out
ENSYNC
TTL In
REFCLK
TTL In
MODE
3-Level In
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| CY7B9910-7SXC | Low Skew Clock Buffer |
| CY7B9910-7SXCT | Low Skew Clock Buffer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B933-155JC | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:HOTLink⑩ Transmitter/Receiver |
| CY7B933-155JI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:HOTLink Transmitter/Receiver |
| CY7B9334 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:SMPTE HOTLink Transmitter/Receiver |
| CY7B933-400JC | 制造商:Cypress Semiconductor 功能描述:PHY 1RX-CH 160Mbps/400Mbps 28-Pin PLCC |
| CY7B933-400JCT | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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