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參數(shù)資料
| 型號： | CY7B9331 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | HOTLink OLC Receiver(熱連接OLC接收器) |
| 中文描述： | 法律顧問室的HOTLink接收器（熱連接法律顧問室接收器） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 112K |
| 代理商： | CY7B9331 |
PRELIMINARY
HOTLink OLC Receiver
CY7B9331
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
April 1994
Features
Fibre Channel compliant
IBM ESCON compliant
OLC Compatible system interface
8B/10B-coded or 10-bit unencoded
160- to 330-Mbps data rate
No external PLL components
Dual ECL 100K serial inputs
Low power: 650 mW
Compatible with fiberoptic modules, coaxial cable, and
twisted pair media
Built-In Self-Test
28-pin SOIC/PLCC
Functional Description
The CY7B9331 HOTLink OLC Receiver is a point-to-point
communications building block that receives data over
high-speed serial links (fiber, coax, and twisted pair) at 160 to
330 Mbits/second. The HOTLink OLC Receiver system inter-
face has been tailored to match OLC (Optical Link Card) timing
and functionality.
The HOTLink receiver accepts the serial bit stream at its dif-
ferential line receiver inputs and, using a completely integrated
PLL clock synchronizer, recovers the timing information nec-
essary for data reconstruction.
The bit stream is deserialized, decoded, and checked for
transmission errors. The recovered byte is presented in paral-
lel to the receiving host along with a byte rate clock.
The 8B/10B encoder/decoder can be disabled in systems that
already encode or scramble the transmitted data. A Built-In
Self-Test pattern generator and checker allows testing of the
transmitter, receiver, and the connecting link as a part of a
system diagnostic check.
The CY7B9331 HOTLink Receiver is a companion part to the
CY7B923 HOTLink Transmitter. The HOTLink chip set pro-
vides a complete physical interface solution. For further infor-
mation on HOTLink Transceiver and Receiver functions see
the CY7B923/933 datasheet.
HOTLink is a trademark of Cypress Semiconductor Corporation.
ESCON is a registered trademark of IBM.
Receiver Logic Block Diagram
B9331–1
ENSYNC
LOOP
INA+
INA
INB(INB+)
SI(INB
)
STATUS
REFCLK
MODE
BISTEN
ECL
TTL
TEST
LOGIC
CLOCK
SYNC
CLK0
SYNC
SC/D (Q
a
)
RVS(Q
j
)
Q
0
7
(Q
b
h
)
OUTPUT
REGISTER
DECODER
DECODER
REGISTER
SHIFTER
FRAMER
DATA
Pin Configurations
SOIC
Top View
INA
INA+
LOOP
BISTEN
ENSYNC
GND
SYNC
GND
V
CCN
RVS(Q
j
)
(Q
h
)Q
7
(Q
g
)Q
6
(Q
f
)Q
5
(Q
i
)Q
4
INB(INB+)
SI(INB
)
MODE
REFCLK
V
CCQ
STATUS
CLK0
V
CCQ
GND
SC/D(Q
a
)
Q
0
(Q
b
)
Q
1
(Q
c
)
Q
2
(Q
d
)
Q
3
(Q
e
)
B9331–2
SC/D(Q
a
)
B9331–3
4 3
1
2
28
8
9
10
11
7
6
5
22
21
20
19
23
24
25
1213
15
14
16
PLCC
Top View
2726
1718
REFCLK
V
STATUS
CLK0
V
GND
ENSYNC
GND
SYNC
GND
V
RVS(Q
j
)
(Q
h
) Q
7
Q
(
Q
(
Q
(
Q
(
Q
(
Q
(
Q
(
B
L
I
I
S
)
M
I
7B9331
6
5
4
3
2
1
0
d
e
i
f
g
c
b
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
24
23
22
21
25
28
27
26
7B9331
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B933-155JC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:HOTLink⑩ Transmitter/Receiver |
| CY7B933-155JI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:HOTLink Transmitter/Receiver |
| CY7B9334 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:SMPTE HOTLink Transmitter/Receiver |
| CY7B933-400JC | 制造商:Cypress Semiconductor 功能描述:PHY 1RX-CH 160Mbps/400Mbps 28-Pin PLCC |
| CY7B933-400JCT | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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