參數(shù)資料
型號(hào)： CY62177DV30L-55BAI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 16-Mbit (2M x 8) Static RAM
中文描述： 2M X 16 STANDARD SRAM, 55 ns, PBGA48
封裝： 8 X 9.50 MM, 1.20 MM HEIGHT, FBGA-48
文件頁(yè)數(shù)： 6/10頁(yè)
文件大?。?/td> 856K
代理商： CY62177DV30L-55BAI
Document #: 001-07721 Rev. *B
Page 6 of 10
CY62168EV30 MoBL
Switching Waveforms
Figure 1
shows address transition controlled read cycle waveforms.
[15, 16]
Figure 1. Read Cycle No. 1
Figure 2
shows OE controlled read cycle waveforms.
[16, 17]
Figure 2. Read Cycle No. 2
PREVIOUS DATA VALID
DATA VALID
RC
t
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
PD
t
HZCE
OE
CE
1
ADDRESS
CE
2
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH
I
CC
I
SB
IMPEDANCE
Notes
15.The device is continuously selected. OE, CE
1
= V
IL
, and CE
2
= V
IH
.
16.WE is HIGH for read cycle.
17.Address valid before or similar to CE
1
transition LOW and CE
2
transition HIGH.
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參數(shù)描述
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