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參數(shù)資料
| 型號： | CY62167DV30 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16-Mbit (1M x 16) Static RAM(16-Mb(1M x 16)靜態(tài)RAM) |
| 中文描述： | 16兆位（1米× 16），靜態(tài)存儲器（16字節(jié)（1米× 16），靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 322K |
| 代理商： | CY62167DV30 |
CY62167DV30 MoBL
Document #: 38-05328 Rev. *G
Page 5 of 12
Data Retention Waveform
[14]
Switching Characteristics
Over the Operating Range
[15]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[18]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
14.BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
15.Test conditions for all parameters other than Tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V
CC(typ)
/2, input pulse levels
of 0 to V
, and output loading of the specified I
OL
/I
as shown in the “AC Test Loads and Waveforms” section.
16.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
17.t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
18.The internal Write time of the memory is defined by the overlap of WE, CE
= V
, BHE and/or BLE = V
, and CE
= V
. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
Description
45 ns
[12]
Min.
55 ns
70 ns
Unit
Max.
Min.
Max.
Min.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
[16]
OE HIGH to High Z
[16, 17]
CE
1
LOW and CE
2
HIGH to Low Z
[16]
CE
1
HIGH and CE
2
LOW to High Z
[16, 17]
CE
1
LOW and CE
2
HIGH to Power-up
CE
1
HIGH and CE
2
LOW to Power-down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[16]
BLE/BHE HIGH to HIGH Z
[16, 17]
45
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
55
70
10
10
10
45
25
55
25
70
35
5
5
5
15
20
25
10
10
10
20
20
25
0
0
0
45
45
55
55
70
70
10
10
10
15
20
25
Write Cycle Time
CE
1
LOW and CE
2
HIGH
to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z
[16, 17]
WE HIGH to Low-Z
[16]
45
40
40
0
0
35
40
25
0
55
40
40
0
0
40
40
25
0
70
60
60
0
0
45
60
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
20
25
10
10
10
V
CC
, min.
t
R
V
CC
, min.
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
CE
1
or
BHE
,
BLE
V
CC
or
CE
2
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