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參數(shù)資料
| 型號： | CY62167DV20LL |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16-Mb (1024K x 16) Static RAM |
| 中文描述： | 16 MB的（1024K × 16）靜態(tài)RAM |
| 文件頁數(shù)： | 5/10頁 |
| 文件大小： | 247K |
| 代理商： | CY62167DV20LL |
CY62167DV20
MoBL2
Document #: 38-05327 Rev. *B
Page 5 of 10
Switching Characteristics
(over the operating range)
[11]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE[10]
t
HZBE
Write Cycle
[14]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Description
CY62167DV20-55
Min.
CY62167DV20-70
Min.
Unit
Max.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW or CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[12]
OE HIGH to High Z
[12, 13]
CE
1
LOW or CE
2
HIGH to Low Z
[12]
CE
1
HIGH or CE
2
LOW to High Z
[12, 13]
CE
1
LOW or CE
2
HIGH to Power-up
CE
1
HIGH or CE
2
LOW to Power-down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[12]
BLE/BHE HIGH to High-Z
[12, 13]
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
70
10
10
55
25
70
35
5
5
20
25
10
10
20
25
0
0
55
55
70
70
10
5
20
25
Write Cycle Time
CE
1
LOW or CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[12, 13]
WE HIGH to Low Z
[12]
55
40
40
0
0
40
45
25
0
70
60
60
0
0
45
60
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
10
10
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[15, 16]
Notes:
11.
Test conditions assume signal transition time of 2 ns or less, timing reference levels of V
CC(typ.)/2
, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
The internal Write time of the memory is defined by the overlap of WE
, CE
1
= V
IL
, BHE and/or BLE = V
IL
.
Device is continuously selected. OE, CE1 = V
IL
, CE2 = V
IH
WE
is HIGH for Read cycle.
12.
13.
14.
15.
16.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
相關PDF資料 |
PDF描述 |
|---|---|
| CY62167DV20LL-55BVI | 16-Mb (1024K x 16) Static RAM |
| CY62167DV20LL-70BVI | 16-Mb (1024K x 16) Static RAM |
| CY62167DV30LL-45ZXI | 16-Mbit (1M x 16) Static RAM |
| CY62167DV30LL-55BVXI | 16-Mbit (1M x 16) Static RAM |
| CY62167DV30LL-55ZXI | 16-Mbit (1M x 16) Static RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY62167DV20LL-55BVI | 制造商:Rochester Electronics LLC 功能描述:16M (1M X 16)- 2.0V SLOW ASYNCH SRAM - Bulk |
| CY62167DV20LL-5BVI | 制造商:Cypress Semiconductor 功能描述: |
| CY62167DV30L-70BVI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 16M-Bit 1M x 16 70ns 48-Pin VFBGA |
| CY62167DV30LL-45ZI | 制造商:Cypress Semiconductor 功能描述: |
| CY62167DV30LL-45ZXI | 功能描述:IC SRAM 16MBIT 45NS 48TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:MoBL® 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
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