參數(shù)資料
型號(hào): CY62167DV20LL
廠商: Cypress Semiconductor Corp.
英文描述: 16-Mb (1024K x 16) Static RAM
中文描述: 16 MB的(1024K × 16)靜態(tài)RAM
文件頁(yè)數(shù): 4/10頁(yè)
文件大?。?/td> 247K
代理商: CY62167DV20LL
CY62167DV20
MoBL2
Document #: 38-05327 Rev. *B
Page 4 of 10
Thermal Resistance
AC Test Loads and Waveforms
Data Retention Waveform
[10]
Parameter
θ
JA
Description
Test Conditions
BGA
55
Unit
C/W
Thermal Resistance (Junction to
Ambient)
[8]
Thermal Resistance (Junction to
Case)
[8]
Still Air, soldered on a 3 x 4.5 inch, two-layer
printed circuit board
θ
JC
16
C/W
V
CC
Typ
V
CC
OUTPUT
R2
C = 30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
Equivalent to:
THéVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Rise Time:
1 V/ns
Fall Time:
1 V/ns
Data Retention Characteristics
Parameter
V
DR
I
CCDR
Description
Conditions
Min.
1.0
Typ.
Max.
2.2
15
10
Unit
V
μ
A
V
CC
for Data Retention
Data Retention Current
V
CC
=1.0V, CE
1
> V
CC
0.2V, CE
2
<
0.2V, V
IN
> V
CC
0.2V or V
IN
< 0.2V
L
LL
t
CDR[8]
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
ns
t
R[9]
t
RC
ns
Parameters
1.8V
UNIT
R1
13500
R2
10800
R
TH
V
TH
6000
0.80
V
Notes:
9.
10.
Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
μ
s or stable at V
CC(min.)
> 100
μ
s.
BHE
.
BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
V
CC(min.)
t
R
V
CC(min.)
t
CDR
V
DR
> 1.0V
DATA RETENTION MODE
CE
or
BHE.BLE
V
CC
CE
2
or
相關(guān)PDF資料
PDF描述
CY62167DV20LL-55BVI 16-Mb (1024K x 16) Static RAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY62167DV20LL-55BVI 制造商:Rochester Electronics LLC 功能描述:16M (1M X 16)- 2.0V SLOW ASYNCH SRAM - Bulk
CY62167DV20LL-5BVI 制造商:Cypress Semiconductor 功能描述:
CY62167DV30L-70BVI 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 16M-Bit 1M x 16 70ns 48-Pin VFBGA
CY62167DV30LL-45ZI 制造商:Cypress Semiconductor 功能描述:
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