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參數(shù)資料
| 型號(hào)： | CY62148DV30L |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mb (512K x 8) MoBL Static RAM |
| 中文描述： | 4 MB的（為512k × 8）的MoBL靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大小： | 195K |
| 代理商： | CY62148DV30L |
CY62148DV30
Document #: 38-05341 Rev. *B
Page 4 of 11
Capacitance
for all packages
[8]
Data Retention Waveform
Parameter
Description
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ.)
Max.
10
10
Unit
pF
pF
C
IN
C
OUT
Input Capacitance
Output Capacitance
Thermal Resistance
Parameter
Θ
JA
Description
Test Conditions
BGA
72
TSOP II
75.13
SOIC
55
STSOP
105
Unit
°
C/W
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 3 x 4.5 inch,
four-layer printed circuit board
Θ
JC
8.86
8.95
22
13
°
C/W
AC Test Loads and Waveforms
R1
Parameters
R1
R2
R
TH
V
TH
2.50V
16667
15385
8000
1.20
3.0V
1103
1554
645
1.75
Unit
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
Conditions
Min. Typ.
[7]
1.5
Max. Unit
V
CC
for Data Retention
Data Retention Current
V
μ
A
μ
A
ns
ns
V
CC
= 1.5V, CE > V
CC
0.2V,
V
IN
> V
CC
0.2V or V
IN
< 0.2V
L
LL
9
6
t
CDR[8]
t
R[9]
Chip Deselect to Data Retention Time
Operation Recovery Time
0
t
RC
V
CC
V
CC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
THé VENIN EQUIVALENT
R
TH
ALL INPUT PULSES
Fall time: 1 V/ns
Rise Time: 1 V/ns
Notes:
8.
9.
Tested initially and after any design or process changes that may affect these parameters.
Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
μ
s or stable at V
CC(min.)
>
100
μ
s.
1.5V
1.5V
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
t
R
CE
V
CC
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|---|---|
| CY62148DV30L-55BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mb (512K x 8) MoBL Static RAM |
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