參數(shù)資料
型號(hào): CY62147EV30
廠商: Cypress Semiconductor Corp.
英文描述: 4-Mbit (256K x 16) Static RAM
中文描述: 4兆位(256K × 16)靜態(tài)RAM
文件頁(yè)數(shù): 4/12頁(yè)
文件大?。?/td> 517K
代理商: CY62147EV30
CY62147EV30 MoBL
Document #: 38-05440 Rev. *E
Page 4 of 12
Thermal Resistance
[9]
Parameter
Description
Test Conditions
VFBGA
Package
75
TSOP II
Package
77
Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
°
C/W
Θ
JC
10
13
°
C/W
AC Test Loads and Waveforms
Figure 1. AC Test Load and Waveforms
Parameters
R1
R2
R
TH
V
TH
2.50V
16667
15385
8000
1.20
3.0V
1103
1554
645
1.75
Unit
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ
[2]
Max Unit
V
DR
I
CCDR[8]
V
CC
for Data Retention
1.5
V
Data Retention Current
V
CC
= 1.5V, CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
Ind’l/Auto-A
0.8
7
μ
A
Auto-E
12
t
CDR [9]
t
R [10]
Chip Deselect to Data Retention Time
0
ns
Operation Recovery Time
t
RC
ns
Data Retention Waveform
[11]
Figure 2. Data Retention Waveform
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT
V
ALL INPUT PULSES
R
TH
R1
Equivalent to: THEVENIN EQUIVALENT
V
CC(min)
t
R
V
CC(min)
t
CDR
V
DR
> 1.5V
DATA RETENTION MODE
V
CC
CE or
BHE.BLE
Notes
10.Full device operation requires linear V
ramp from V
to V
> 100
μ
s or stable at V
> 100
μ
s.
11. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
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