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參數(shù)資料
| 型號(hào)： | CY62147EV30 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mbit (256K x 16) Static RAM |
| 中文描述： | 4兆位（256K × 16）靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 517K |
| 代理商： | CY62147EV30 |
CY62147EV30 MoBL
Document #: 38-05440 Rev. *E
Page 3 of 12
Maximum Ratings
Exceeding the maximum ratings may shorten the battery life
of the device. User guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Supply Voltage to Ground
Potential ............................ –0.3V to + 3.9V (V
CCmax
+ 0.3V)
DC Voltage Applied to Outputs
in High-Z State
[5, 6]
................–0.3V to 3.9V (V
CCmax
+ 0.3V)
DC Input Voltage
[5, 6]
............–0.3V to 3.9V (V
CCmax
+ 0.3V)
Electrical Characteristics
Over the Operating Range
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage .......................................... >2001V
(MIL-STD-883, Method 3015)
Latch up Current......................................................>200 mA
Operating Range
Device
Range
Ambient
Temperature
V
CC
[7]
CY62147EV30LL Ind’l/Auto-A –40°C to +85°C
Auto-E
2.2V to
3.6V
–40°C to +125°C
Parameter
Description
Test Conditions
45 ns (Ind’l/Auto-A)
Min
Typ
[2]
2.0
2.4
55 ns (Auto-E)
Min
Typ
[2]
2.0
2.4
Unit
Max
Max
V
OH
Output HIGH
Voltage
I
OH
= –0.1 mA
I
OH
= –1.0 mA, V
CC
> 2.70V
I
OL
= 0.1 mA
I
OL
= 2.1 mA, V
CC
= 2.70V
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
GND < V
I
< V
CC
V
V
V
V
V
V
V
V
μ
A
V
OL
Output LOW
Voltage
0.4
0.4
0.4
0.4
V
IH
Input HIGH
Voltage
1.8
2.2
–0.3
–0.3
–1
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+1
1.8
2.2
–0.3
–0.3
–4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+4
V
IL
Input LOW
Voltage
I
IX
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
I
OZ
GND < V
O
< V
CC
, Output Disabled
–1
+1
–4
+4
μ
A
I
CC
f = f
max
= 1/t
RC
V
CC
= V
CC(max)
f = 1 MHz
I
OUT
= 0 mA
CMOS levels
15
2
20
2.5
15
2
25
3
mA
I
SB1
Automatic CE
Power Down
Current —
CMOS Inputs
CE > V
CC
– 0.2V
V
IN
> V
CC
– 0.2V, V
IN
< 0.2V
f = f
max
(Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
V
CC
= 3.60V
CE > V
CC
– 0.2V
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= 3.60V
1
7
1
20
μ
A
I
SB2 [8]
Automatic CE
Power Down
Current —
CMOS Inputs
1
7
1
20
μ
A
Capacitance
For all packages.
[9]
Parameter
Description
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
C
IN
C
OUT
Input Capacitance
Output Capacitance
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
6. V
= V
+ 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100
μ
s ramp time from 0 to V
(min) and 200
μ
s wait time after V
stabilization.
8. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
[+] Feedback
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