參數(shù)資料
型號(hào): CY62138CV25LL-55BAI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 2M (256K x 8) Static RAM
中文描述: 256K X 8 STANDARD SRAM, 55 ns, PBGA36
封裝: 7 X 7 MM, 1.20 MM HEIGHT, FBGA-36
文件頁(yè)數(shù): 6/12頁(yè)
文件大?。?/td> 234K
代理商: CY62138CV25LL-55BAI
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Document #: 38-05200 Rev. *D
Page 6 of 12
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[9, 10]
WE HIGH to Low-Z
[9]
45
0
0
40
25
0
60
0
0
45
30
0
ns
ns
ns
ns
ns
ns
ns
ns
20
25
10
10
Switching Characteristics
Over the Operating Range
[8]
(continued)
Parameter
Description
55 ns
70 ns
Unit
Min.
Max.
Min.
Max.
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[12, 13]
Notes:
12. Device is continuously selected. OE, CE
1
= V
IL
, CE
2
=V
IH
.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE
1
transition LOW and CE
2
transition HIGH.
ADDRESS
DATA OUT
PREVIOUS
DATA VALID
t
RC
t
AA
t
OHA
DATA VALID
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
1
I
CC
I
SB
IMPEDANCE
ADDRESS
CE
2
DATA OUT
V
CC
SUPPLY
CURRENT
Read Cycle No. 2 (OE Controlled)
[13, 14]
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