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參數(shù)資料
| 型號： | CY62138CV25LL-55BAI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2M (256K x 8) Static RAM |
| 中文描述： | 256K X 8 STANDARD SRAM, 55 ns, PBGA36 |
| 封裝： | 7 X 7 MM, 1.20 MM HEIGHT, FBGA-36 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 234K |
| 代理商： | CY62138CV25LL-55BAI |
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Document #: 38-05200 Rev. *D
Page 5 of 12
Parameters
R1
R2
R
TH
V
TH
Data Retention Characteristics
(Over the Operating Range)
2.5V
16600
15400
8000
1.20
3.0V
1105
1550
645
1.75
3.3V
1216
1374
645
1.75
Unit
V
Parameter
V
DR
I
CCDR
Description
Conditions
Min.
1.5
Typ.
[5]
Max.
V
CC(max.)
6
Unit
V
μ
A
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.5V
CE
1
> V
CC
–
0.2V or CE
2
< 0.2V
V
IN
> V
CC
0.2V or V
IN
< 0.2V
1
t
CDR[6]
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
ns
t
R[7]
Data Retention Waveform
t
RC
Switching Characteristics
Over the Operating Range
[8]
Parameter
Description
55 ns
70 ns
Unit
Min.
Max.
Min.
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[11]
t
WC
t
SCE
Notes:
7.
Full-device AC operation requires linear V
ramp from V
to V
> 100
μ
s or stable at V
> 100
μ
s.
8.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
/I
and 30-pF load capacitance.
9.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
HZWE
is less than t
LZWE
for any given device.
10. t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
11.
The internal write time of the memory is defined by the overlap of WE, CE
= V
, and CE
= V
. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[9]
OE HIGH to High-Z
[9, 10]
CE
1
LOW and CE
2
HIGH to Low-Z
[9]
CE
1
HIGH or CE
2
LOW to High-Z
[9, 10]
CE
1
LOW and CE
2
HIGH to Power-up
CE
1
HIGH or CE
2
LOW to Power-down
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
70
10
10
55
25
70
35
5
5
20
25
10
10
20
25
0
0
55
70
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
55
45
70
60
ns
ns
V
CC(min.)
t
R
V
CC(min.)
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
CE
1
or
V
CC
CE
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62138CV25LL-55BVI | 2M (256K x 8) Static RAM |
| CY62138CV25LL-70BAI | 2M (256K x 8) Static RAM |
| CY62138CV25LL-70BVI | 2M (256K x 8) Static RAM |
| CY62138CV30 | 2M (256K x 8) Static RAM |
| CY62138CV30LL-55BAI | 2M (256K x 8) Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62138CV25LL-55BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2M (256K x 8) Static RAM |
| CY62138CV25LL-70BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2M (256K x 8) Static RAM |
| CY62138CV25LL-70BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2M (256K x 8) Static RAM |
| CY62138CV30 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2M (256K x 8) Static RAM |
| CY62138CV30LL-55BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2M (256K x 8) Static RAM |
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