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參數(shù)資料
| 型號(hào)： | CY62128BNLL-70SXA |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1-Mbit (128K x 8) Static RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 70 ns, PDSO32 |
| 封裝： | 0.450 INCH, LEAD FREE, SOIC-32 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 589K |
| 代理商： | CY62128BNLL-70SXA |
CY62128BN
MoBL
Document #: 001-06498 Rev. *A
Page 5 of 12
Switching Characteristics
[7]
Over the Operating Range
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[10]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Description
CY62128BN-55
Min.
CY62128BN-70
Min.
Unit
Max.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid, CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[7, 9]
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[9]
CE
1
HIGH to High Z, CE
2
LOW to High Z
[8, 9]
CE
1
LOW to Power-up, CE
2
HIGH to Power-up
CE
1
HIGH to Power-down, CE
2
LOW to Power-down
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
70
5
5
55
20
70
35
0
0
20
25
5
5
20
25
0
0
55
70
Write Cycle Time
CE
1
LOW to Write End, CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low Z
[9]
WE LOW to High Z
[8, 9]
55
45
45
0
0
45
25
0
5
70
60
60
0
0
50
30
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
Switching Waveforms
Read Cycle No.1
[11, 12]
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
8. t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
9. At any given temperature and voltage condition, t
is less than t
LZCE
, t
is less than t
, and t
is less than t
for any given device.
10.The internal write time of the memory is defined by the overlap of CE
LOW, CE
HIGH, and WE LOW. CE
and WE must be LOW and CE
HIGH to initiate a
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
11. Device is continuously selected. OE, CE
1
= V
IL
, CE
2
= V
IH
.
12.WE is HIGH for read cycle.
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
[+] Feedback
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| CY62128BNLL-70SXE | 1-Mbit (128K x 8) Static RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62128BNLL-70SXAT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 SLO 5.0V SUPER LO PWR 128K X 8 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62128BNLL-70SXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62128BNLL-70SXCT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62128BNLL-70SXE | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 SLO 5.0V SUPER LO PWR 128K X 8 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62128BNLL-70SXET | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 SLO 5.0V SUPER LO PWR 128K X 8 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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