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參數(shù)資料
| 型號(hào)： | CY62126V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 16 Static RAM(64K x 16 靜態(tài)RAM) |
| 中文描述： | 64K的× 16靜態(tài)RAM（64K的× 16靜態(tài)RAM）的 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 150K |
| 代理商： | CY62126V |
CY62126V
PRELIMINARY
4
Switching Characteristics
[5]
Over the Operating Range
62126V
–
55
Min.
62126V
–
70
Min.
Parameter
Description
Max.
Max.
Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
[8]
Read Cycle Time
55
70
ns
Address to Data Valid
55
70
ns
Data Hold from Address Change
10
10
ns
CE LOW to Data Valid
55
70
ns
OE LOW to Data Valid
OE LOW to Low Z
[7]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[7]
CE HIGH to High Z
[6, 7]
35
ns
5
5
ns
20
25
ns
10
10
ns
20
25
ns
CE LOW to Power-Up
0
0
ns
CE HIGH to Power-Down
55
70
ns
Byte Enable to Data Valid
Byte Enable to LOW Z
[7]
Byte Disable to HIGH Z
[6,7]
25
35
ns
5
5
ns
20
25
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Shaded areas contain advance information.
Note:
5.
Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30pF load capacitance.
6.
t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
7.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, t
HZWE
is less than t
LZWE
, and t
HZBE
is less than t
LZBE
, for any given
device.
8.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Refer to truth
table for further conditions from BHE and BLE.
Write Cycle Time
55
70
ns
CE LOW to Write End
45
60
ns
Address Set-Up to Write End
45
60
ns
Address Hold from Write End
0
0
ns
Address Set-Up to Write Start
0
0
ns
WE Pulse Width
40
50
ns
Data Set-Up to Write End
25
30
ns
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6,7]
0
0
ns
5
5
ns
25
25
ns
Byte Enable to End of Write
45
60
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62127BV | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 16 Static RAM |
| CY62127BV_02 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1M (64K x 16) Static RAM |
| CY62127BVLL-55BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 16 Static RAM |
| CY62127BVLL-55ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 16 Static RAM |
| CY62127BVLL-70BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 16 Static RAM |
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