參數(shù)資料
型號： CY39200Z388-167MGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 8.5 ns, PBGA388
封裝： BGA-388
文件頁數(shù)： 5/57頁
文件大?。?/td> 1166K
代理商： CY39200Z388-167MGC
PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 13 of 57
Timing Model
One important feature of the Delta39K family is the simplicity
of its timing. All combinatorial and registered/synchronous de-
lays are worst case and system performance is static (as
shown in the AC specs section) as long as data is routed
through the same horizontal and vertical channels. Figure 10
illustrates the true timing model for the 200-MHz devices. For
synchronous clocking of macrocells, a delay is incurred from
macrocell clock to macrocell clock of separate Logic Blocks
within the same cluster, as well as separate Logic Blocks with-
in different clusters. This is respectively shown as tSCS and
tSCS2 in Figure 10. For combinatorial paths, any input to any
output (from corner to corner on the device), incurs a worst-
case delay in the 39K100 regardless of the amount of logic or
which horizontal and vertical channels are used. This is the tPD
shown in Figure 10. For synchronous systems, the input set-
up time to the output macrocell register and the clock to output
time are shown as the parameters tMCS and tMCCO shown in
the Figure 10. These measurements are for any output and
synchronous clock, regardless of the logic placement.
The Delta39K features:
no dedicated vs. I/O pin delays
no penalty for using 0–16 product terms
no added delay for steering product terms
no added delay for sharing product terms
no output bypass delays
The simple timing model of the Delta39K family eliminates un-
expected performance penalties.
Figure 10. Timing Model for 39K100 Device
Channel
RAM
4
GCLK[3:0]
LB 0
PIM
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
RAM
Channel
RAM
4
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
4
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
4
LB 0
PIM
8 Kb
SRAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
8 Kb
SRAM
Channel
RAM
4
GCLK[3:0]
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
4
LB 0
PIM
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
4
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
4
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
4
GCLK[3:0]
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
4
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
4
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
4
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
Channel
RAM
Cluster
tMCS
tPD
tSCS
tMCCO
tSCS2
相關(guān)PDF資料
PDF描述
CY39200Z484-167BBC LOADABLE PLD, 8.5 ns, PBGA484
CY39200Z676-167MBC LOADABLE PLD, 8.5 ns, PBGA676
CY39100V388B-125MGXC LOADABLE PLD, 10 ns, PBGA388
CY39100V388B-83MGXC LOADABLE PLD, 15 ns, PBGA388
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39200Z388-233MGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200Z388-233MGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200Z484-125BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200Z484-125BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200Z676-125BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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