參數(shù)資料
型號(hào)： CY39200V676-167MBC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 8.5 ns, PBGA676
封裝： 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-676
文件頁數(shù)： 34/57頁
文件大?。?/td> 1166K
代理商： CY39200V676-167MBC
PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 4 of 57
General Description
The Delta39K family, based on a 0.18
m, 6-layer metal
CMOS logic process, offers a wide range of high-density solu-
tions at unparalleled system performance. The Delta39K fam-
ily is designed to combine the high speed, predictable timing,
and ease of use of CPLDs with the high densities and low
power of FPGAs. With devices ranging from 15,000 to 350,000
usable gates, the family features devices ten times the size of
previously available CPLDs. Even at these large densities, the
Delta39K family is fast enough to implement a fully synthesiz-
able 64-bit, 66-MHz PCI core.
The architecture is based on Logic Block Clusters (LBC) that
are connected by Horizontal and Vertical (H&V) routing chan-
nels. Each LBC features eight individual Logic Blocks (LB) and
two cluster memory blocks. Adjacent to each LBC is a channel
memory block, which can be accessed directly from the I/O
pins. Both types of memory blocks are highly configurable and
can be cascaded in width and depth. See Figure 1 for a block
diagram of the Delta39K architecture.
All the members of the Delta39K family have Cypress’s highly
regarded In-System Reprogrammability (ISR) feature, which
simplifies both design and manufacturing flows, thereby re-
ducing costs. The ISR feature provides the ability to reconfig-
ure the devices without having design changes cause pinout
or timing changes in most cases. The Cypress ISR function is
implemented through a JTAG-compliant serial interface. Data
is shifted in and out through the TDI and TDO pins respective-
ly. Superior routability, simple timing, and the ISR allows users
to change existing logic designs while simultaneously fixing
pinout assignments and maintaining system performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification, meet-
ing the electrical and timing requirements. The Delta39K fam-
ily also features user programmable bus-hold and slew rate
control capabilities on each I/O pin.
AnyVolt Interface
All Delta39KV devices feature an on-chip regulator, which ac-
cepts 3.3V or 2.5V on the VCC supply pins and steps it down
to 1.8V internally, the voltage level at which the core operates.
The Delta39KZ devices accept 1.8V on the VCC supply pins
directly. With Delta39K’s AnyVolt technology, the I/O pins can
be connected to either 1.8V, 2.5V, or 3.3V. All Delta39K devic-
es are 3.3V tolerant regardless of VCCIO or VCC settings.
Global Routing Description
The routing architecture of the Delta39K is made up of hori-
zontal and vertical (H&V) routing channels. These routing
channels allow signals from each of the Delta39K architectural
components to communicate with one another. In addition to
the horizontal and vertical routing channels that interconnect
the I/O banks, channel memory blocks, and logic block clus-
ters, each LBC contains a Programmable Interconnect Matrix
(PIM), which is used to route signals among the logic blocks
and the cluster memory blocks.
Figure 2 is a block diagram of the routing channels that inter-
face within the Delta39K architecture. The LBC is exactly the
same for every member of the Delta39K CPLD family.
Logic Block Cluster (LBC)
The Delta39K architecture consists of several logic block clus-
ters, each of which have 8 Logic Blocks (LB) and 2 cluster
memory blocks connected via a Programmable Interconnect
Matrix (PIM) as shown in Figure 3. Each cluster memory block
consists of 8-Kbit single-port RAM, which is configurable as
synchronous or asynchronous. The cluster memory blocks
can be cascaded with other cluster memory blocks within the
same LBC as well as other LBCs to implement larger memory
functions. If a cluster memory block is not specifically utilized
by the designer, Cypress’s Warp software can automatically
use it to implement large blocks of logic.
All LBCs interface with each other via horizontal and vertical
routing channels.
Note:
5.
For HSTL only.
Device
VCC
VCCIO
39KV
3.3V or 2.5V
3.3V or 2.5V or 1.8V or 1.5V[5]
39KZ
1.8V
3.3V or 2.5V or 1.8V or 1.5V[5]
Figure 2. Delta39K Routing Interface
LB
Cluster
PIM
Cluster
Memory
Block
LB
Cluster
Memory
Block
LB
Channel
Memory
Block
I/O Block
I/O
B
lock
Channel memory
outputs drive
dedicated tracks in the
horizontal and vertical
routing channels
H-to-V
PIM
V-to-H
PIM
Pin inputs from the I/O cells
drive dedicated tracks in the
horizontal and vertical routing
channels
72
64
相關(guān)PDF資料
PDF描述
CY39200Z208-167NC LOADABLE PLD, 8.5 ns, PQFP208
CY39200Z388-167MGC LOADABLE PLD, 8.5 ns, PBGA388
CY39200Z484-167BBC LOADABLE PLD, 8.5 ns, PBGA484
CY39200Z676-167MBC LOADABLE PLD, 8.5 ns, PBGA676
CY39100V388B-125MGXC LOADABLE PLD, 10 ns, PBGA388
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39200V676-181MBC 制造商:Cypress Semiconductor 功能描述:
CY39200V676-181MBXC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Delta39K 200K 181MHz COM RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
CY39200V676-83MBXC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Delta39K 200K 83MHz COM RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
CY39200Z208-125BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200Z208-125BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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