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參數(shù)資料
| 型號： | CY39050V208-125NTXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, 10 ns, PQFP208 |
| 封裝： | 28 X 28 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, EQFP-208 |
| 文件頁數(shù)： | 56/86頁 |
| 文件大?。?/td> | 2802K |
| 代理商： | CY39050V208-125NTXC |
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Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *I
Page 6 of 86
Macrocell
Within each logic block there are 16 macrocells. Each
macrocell accepts a sum of up to 16 product terms from the
product term array. The sum of these 16 product terms can be
output in either registered or combinatorial mode. Figure 4
displays the block diagram of the macrocell. The register can
be asynchronously preset or asynchronously reset at the
macrocell level with the separate preset and reset product
terms. Each of these product terms features programmable
polarity. This allows the registers to be preset or reset based
on an AND expression or an OR expression.
An XOR gate in the Delta39K macrocell allows for many
different types of equations to be realized. It can be used as a
polarity mux to implement the true or complement form of an
equation in the product term array or as a toggle to turn the D
flip-flop into a T flip-flop. The carry-chain input mux allows
additional flexibility for the implementation of different types of
logic. The macrocell can utilize the carry chain logic to
implement adders, subtractors, magnitude comparators,
parity tree, or even generic XOR logic. The output of the
macrocell is either registered or combinatorial.
Carry Chain Logic
The Delta39K macrocell features carry chain logic which is
used for fast and efficient implementation of arithmetic opera-
tions. The carry logic connects macrocells in up to four logic
blocks for a total of 64 macrocells. Effective data path opera-
tions are implemented through the use of carry-in arithmetic,
which drives through the circuit quickly. Figure 4 shows that
the carry chain logic within the macrocell consists of two
product terms (CPT0 and CPT1) from the PTA and an input
carry-in for carry logic. The inputs to the carry chain mux are
connected directly to the product terms in the PTA. The output
of the carry chain mux generates the carry-out for the next
macrocell in the logic block as well as the local carry input that
is connected to an input of the XOR input mux. Carry-in and a
configuration bit are inputs to an AND gate. This AND gate
provides a method of segmenting the carry chain in any
macrocell in the logic block.
Macrocell Clocks
Clocking of the register is highly flexible. Four global
synchronous clocks (GCLK[3:0]) and a PTCLK are available
at each macrocell register. Furthermore, a clock polarity mux
within each macrocell allows the register to be clocked on the
rising or the falling edge (see macrocell diagram in Figure 4).
PRESET/RESET Configurations
The macrocell register can be asynchronously preset and
reset using the PRESET and RESET mux. Both signals are
active high and can be controlled by either of two Preset/Reset
product terms (PRC[1:0] in Figure 4) or GND. In situations
where the PRESET and RESET are active at the same time,
RESET takes priority over PRESET.
D
Q
PSET
RES
GCLK[3:0]
PTCLK
FROM PTM
CPT0
CPT1
PRC[1:0]
0
1
0
1
To PIM
C
Carry Out
(to macrocell n+1)
Carry In
(from macrocell n-1)
Up To 16 PTs
PRESET
Mux
Clock
Polarity
Mux
RESET
Mux
Clock Mux
Carry Chain
Mux
XOR Input
Mux
Output
Mux
Q
C
3
2
3
C
Figure 4. Delta39K Macrocell
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| CY39050V208-233NTXC | LOADABLE PLD, 7.2 ns, PQFP208 |
| CY39050V208-83NTXC | LOADABLE PLD, 15 ns, PQFP208 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY39050V208-125NTXI | 功能描述:IC CPLD 50K GATE 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Delta 39K™ ISR™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| CY39050V208-181BBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050V208-181BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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