參數(shù)資料
型號(hào)： CY39050V208-125NTXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： PLD
英文描述： LOADABLE PLD, 10 ns, PQFP208
封裝： 28 X 28 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, EQFP-208
文件頁(yè)數(shù)： 45/86頁(yè)
文件大小： 2802K
代理商： CY39050V208-125NTXC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *I
Page 5 of 86
Logic Block
The LB is the basic building block of the Delta39K architecture.
It consists of a product term array, an intelligent product-term
allocator, and 16 macrocells.
Product Term Array
Each logic block features a 72 x 83 programmable product
term array. This array accepts 36 inputs from the PIM. These
inputs originate from device pins and macrocell feedbacks as
well as cluster memory and channel memory feedbacks.
Active LOW and active HIGH versions of each of these inputs
are generated to create the full 72-input field. The 83 product
terms in the array can be created from any of the 72 inputs.
Of the 83 product terms, 80 are for general-purpose use for
the 16 macrocells in the logic block. Two of the remaining three
product terms in the logic block are used as asynchronous set
and asynchronous reset product terms. The final product term
is the Product Term clock (PTCLK) and is shared by all 16
macrocells within a logic block.
Product Term Allocator
Through the product term allocator, Warp software automati-
cally distributes the 80 product terms as needed among the 16
macrocells in the logic block. The product term allocator
provides two important capabilities without affecting perfor-
mance: product term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed. For example, if one macrocell
requires ten product terms while another needs just three, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On Delta39K devices,
product terms are steered on an individual basis. Any number
between 1 and 16 product terms can be steered to any
macrocell.
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than
one function has one or more product terms in its equation that
are common to other functions, those product terms are only
programmed once. The Delta39K product term allocator
allows sharing across groups of four macrocells in a variable
fashion. The software automatically takes advantage of this
capability so that the user does not have to intervene.
Note that neither product term sharing nor product term
steering have any effect on the speed of the product. All
steering and sharing configurations have been incorporated in
the timing specifications for the Delta39K devices.
.
Logic
Block
0
Logic
Block
1
Logic
Block
3
Logic
Block
2
Cluster
Memory
0
PIM
Logic
Block
7
Logic
Block
6
Logic
Block
4
Logic
Block
5
Cluster
Memory
1
64 Inputs From
Horizontal Routing
Channel
64 Inputs From
Vertical Routing
Channel
144 Outputs to
Horizontal and Vertical
cluster-to-channel PIMs
Clock Inputs
GCLK[3:0]
CC
CC = Carry Chain
16
36
16
36
16
36
16
36
16
36
16
36
16
36
8
25
8
25
4
16
36
Figure 3. Delta39K Logic Block Cluster Diagram
相關(guān)PDF資料
PDF描述
CY39050V208-125NTXI LOADABLE PLD, 10 ns, PQFP208
CY39050V208-233NTXC LOADABLE PLD, 7.2 ns, PQFP208
CY39050V208-83NTXC LOADABLE PLD, 15 ns, PQFP208
CY39050V208-83NTXI LOADABLE PLD, 15 ns, PQFP208
CY39200V208-181NTXC LOADABLE PLD, 8.5 ns, PQFP208
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39050V208-125NTXI 功能描述:IC CPLD 50K GATE 208BQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Delta 39K™ ISR™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類(lèi)型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門(mén)數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤(pán)
CY39050V208-181BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39050V208-181BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39050V208-181BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39050V208-181BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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