參數(shù)資料
型號(hào)： CY37128
廠商： Cypress Semiconductor Corp.
英文描述： 5V, 3.3V, ISR High-Performance CPLDs(5V, 3.3V, ISR 高性能CPLD)
中文描述： 為5V，3.3V，ISR的高性能CPLD的（為5V，3.3V，ISR的高性能的CPLD）
文件頁數(shù)： 19/65頁
文件大?。?/td> 1184K
代理商： CY37128
Ultra37000
CPLD Family
[1]
19
Switching Characteristics
Over the Operating Range
[11]
Parameter
Combinatorial Mode Parameters
t
PD[12, 13, 14]
t
PDL[12, 13, 14]
t
PDLL[12, 13, 14]
t
EA[12, 13, 14]
t
ER[10, 12]
Input Register Parameters
Description
Unit
Input to Combinatorial Output
Input to Output Through Transparent Input or Output Latch
ns
ns
Input to Output Through Transparent Input and Output Latches
ns
Input to Output Enable
Input to Output Disable
ns
ns
t
WL
t
WH
t
IS
t
IH
t
ICO[12, 13, 14]
t
ICOL[12, 13, 14]
Synchronous Clocking Parameters
t
CO[13, 14]
t
S[12]
t
H
t
CO2[12, 13, 14]
Clock or Latch Enable Input LOW Time
[9]
Clock or Latch Enable Input HIGH Time
[9]
ns
ns
Input Register or Latch Set-Up Time
ns
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to Combinatorial Output
ns
ns
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
ns
Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output
Set-Up Time from Input to Sync. Clk (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
Register or Latch Data Hold Time
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Combinatorial Output
Delay (Through Logic Array)
ns
ns
ns
ns
t
SCS[12]
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output Synchronous
Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable (Through Logic Array)
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK
0
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK
0
,
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
Product Term Clocking Parameters
t
COPT[12, 13, 14]
Product Term Clock or Latch Enable (PTCLK) to Output
t
SPT
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)
t
HPT
Register or Latch Data Hold Time
t
ISPT[12]
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK)
ns
t
SL[12]
ns
t
HL
ns
ns
ns
ns
ns
t
IHPT
t
CO2PT[12, 13, 14]
Buried Register Used as an Input Register or Latch Data Hold Time
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
ns
ns
Pipelined Mode Parameters
t
ICS[12]
Input Register Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) to Output Register Synchronous
Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
)
ns
Notes:
11. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
12. Logic Blocks operating in Low-Power Mode, add t
to this spec.
13. Outputs using Slow Output Slew Rate, add t
SLEW
to this spec.
14. When V
CCO
= 3.3V, add t
3.3IO
to this spec.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY37128P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Logic
CY37128P100-100AC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
CY37128P100-100AI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
CY37128P100-100AXC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 Macrocell 5V COM RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
CY37128P100-100AXI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
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