參數(shù)資料
型號(hào)： CY37128
廠商： Cypress Semiconductor Corp.
英文描述： 5V, 3.3V, ISR High-Performance CPLDs(5V, 3.3V, ISR 高性能CPLD)
中文描述： 為5V，3.3V，ISR的高性能CPLD的（為5V，3.3V，ISR的高性能的CPLD）
文件頁數(shù)： 15/65頁
文件大?。?/td> 1184K
代理商： CY37128
Ultra37000
CPLD Family
[1]
15
5.0V Device Electrical Characteristics
Over the Operating Range
Parameter
V
OH
Description
Test Conditions
I
OH
=
–
3.2 mA (Com
’
l/Ind)
[5]
I
OH
=
–
2.0 mA (Mil)
[5]
I
OH
= 0
μ
A (Com
’
l)
[6]
I
OH
= 0
μ
A (Ind/Mil)
[6]
I
OH
=
–
100
μ
A (Com
’
l)
[6]
I
OH
=
–
150
μ
A (Ind/Mil)
[6]
I
OL
= 16 mA (Com
’
l/Ind)
[5]
I
OL
= 12 mA (Mil)
[5]
Guaranteed Input Logical HIGH Voltage
for all Inputs
[7]
Guaranteed Input Logical LOW Voltage
for all Inputs
[7]
V
I
= GND OR V
CC
, Bus-Hold Disabled
V
O
= GND or V
CC
, Output Disabled,
Bus-Hold Disabled
V
CC
= Max., V
O
= 3.3V, Output
Disabled
[7]
, Bus-Hold Enabled
V
CC
= Max., V
OUT
= 0.5V
Min.
2.4
Typ.
Max.
Unit
V
Output HIGH Voltage
V
CC
= Min.
2.4
V
V
V
V
V
OHZ
Output HIGH Voltage with
Output Disabled
[9]
V
CC
= Max.
4.2
4.5
3.6
3.6
0.5
0.5
V
V
V
V
V
OL
Output LOW Voltage
V
CC
= Min.
V
IH
Input HIGH Voltage
2.0
V
CCmax
V
IL
Input LOW Voltage
–
0.5
0.8
V
I
IX
I
OZ
Input Load Current
–
10
10
μ
A
μ
A
Output Leakage Current
–
50
50
I
OZBH
Output Leakage Current
0
70
125
μ
A
I
OS
Output Short Circuit
Current
[8, 9]
Input Bus-Hold LOW
Sustaining Current
Input Bus-Hold HIGH
Sustaining Current
Input Bus-Hold LOW Overdrive
Current
Input Bus-Hold HIGH Overdrive
Current
–
30
–
160
mA
I
BHL
V
CC
= Min., V
IL
= 0.8V
+75
μ
A
I
BHH
V
CC
= Min., V
IH
= 2.0V
–
75
μ
A
I
BHLO
V
CC
= Max.
+500
μ
A
I
BHHO
V
CC
= Max.
–
500
μ
A
Inductance
[9]
Parameter
L
Description
Maximum Pin
Inductance
Test
Conditions
V
IN
= 5.0V
at f = 1 MHz
44-
Lead
TQFP
2
44-
Lead
PLCC
5
44-
Lead
CLCC
2
84-
Lead
PLCC
8
84-
Lead
CLCC
5
100-
Lead
TQFP
8
160-
Lead
TQFP
9
208-
Lead
PQFP
11
Unit
nH
Capacitance
[9]
Parameter
Description
Test Conditions
Max.
Unit
C
I/O
C
CLK
Input/Output Capacitance
V
IN
= 5.0V at f = 1 MHz at T
A
= 25
°
C
V
IN
= 5.0V at f = 1 MHz at T
A
= 25
°
C
8
pF
Clock Signal Capacitance
12
pF
Endurance Characteristics
[9]
Parameter
Description
Test Conditions
Min.
Typ.
Unit
N
Minimum Reprogramming Cycles
Normal Programming Conditions
[3]
1,000
10,000
Cycles
Notes:
5.
6.
I
=
–
2
mA, I
= 2 mA for TDO.
When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered
significantly by a small leakage current. Note that all I/Os are output disabled during ISR programming. Refer to the application note
“
Understanding Bus-
Hold
”
for additional information.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
OUT
= 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect these parameters.
7.
8.
9.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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CY37128P100-100AC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
CY37128P100-100AI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
CY37128P100-100AXC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 Macrocell 5V COM RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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