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參數(shù)資料
| 型號： | CY3692 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | SCREWDRIVER, XONIC SLOT 3 X 100SCREWDRIVER, XONIC SLOT 3 X 100; Tip Size A x B:3 x 0.5mm; Tip size:3mm; Length, blade:100mm; Length, Inches:4"; Handle type:SHATTERPROOF CELLULOSE ACETATE; Tip Size:3 mm; Tip type:Parallel Slot |
| 中文描述： | 200 - MHz的現(xiàn)場可編程零延遲緩沖器 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 201K |
| 代理商： | CY3692 |
CY23FP12
Document #: 38-07246 Rev. *E
Page 7 of 10
Switching Characteristics
[5]
Parameter
Description
Test Conditions
Min.
10
1
25
10
10
10
10
45.0
40.0
Typ.
Max.
200
Unit
MHz
V/ns
%
MHz
Reference Frequency
[6]
Reference Edge Rate
Reference Duty Cycle
Output Frequency
[7]
75
200
166.7
100
83.3
55.0
60.0
1.6
t
1
C
L
= 15 pF, Commercial Temperature
C
L
= 15 pF, Industrial Temperature
C
L
= 30 pF, Commercial Temperature
C
L
= 30 pF, Industrial Temperature
V
DDA/B
= 3.3V, measured at V
DD
/2
V
DDA/B
= 2.5V
V
DDA/B
= 3.3V, 0.8V to 2.0V,
C
L
= 30 pF (standard drive and high drive)
V
DDA/B
= 3.3V, 0.8V to 2.0V,
C
L
= 15 pF (standard drive and high drive)
V
DDA/B
= 2.5V, 0.6V to 1.8V,
C
L
= 30 pF (high drive only)
V
DDA/B
= 2.5V, 0.6V to 1.8V,
C
L
= 15 pF (high drive only)
V
DDA/B
= 3.3V, 0.8V to 2.0V,
C
L
= 30 pF (standard drive and high drive)
V
DDA/B
= 3.3V, 0.8V to 2.0V,
C
L
= 15 pF (standard drive and high drive)
V
DDA/B
= 2.5V, 0.6V to 1.8V,
C
L
= 30 pF (high drive only)
V
DDA/B
= 2.5V, 0.6V to 1.8V,
C
L
= 15 pF (high drive only)
Outputs @200 MHz, tracking skew not
included
Duty Cycle
[5]
50.0
50.0
%
t
3
Rise Time
[5]
ns
0.8
2.0
1.0
t
4
Fall Time
[5]
1.6
ns
0.8
1.6
0.8
TTB
Total Timing Budget,
[8,9]
Bank A and B same
frequency
Total Timing Budget, Bank
A and B different frequency
Output to Output Skew
[5]
Bank to Bank Skew
Bank to Bank Skew
Bank to Bank Skew
Input to Output Skew (static
phase offset)
[5]
Device to Device Skew
[5]
Cycle to Cycle Jitter
[5]
(Peak)
Cycle to Cycle Jitter
[5]
(Peak)
650
ps
850
t
5
All outputs equally loaded
Same frequency
Different frequency
Different voltage, same frequency
Measured at V
DD
/2, REF to FBK
35
[10]
200
200
400
400
250
ps
t
6
0
ps
t
7
t
J
Measured at V
DD
/2
Bank A and B same frequency
0
500
200
ps
ps
110
[11]
Bank A and B different frequency
400
Notes:
5. All parameters are specified with loaded outputs.
6. When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the reference frequency can be lower than 10MHz. With auto power-down
disabled and PLL power-down enabled, the reference frequency can be as low as DC level.
7. When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the output frequency can be lower than 10MHz. With auto power-down
disabled and PLL power-down enabled, the output frequency can be as low as DC level.
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew,
cycle-cycle jitter, and dynamic phase error.TTB will be equal to or smaller than the maximum specified value at a given frequency.
10.Same frequency, 15pF load, high drive.
11. Same frequency, 15pF load, low drive.
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