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參數(shù)資料
| 型號： | CY2PD817 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 55K |
| 代理商： | CY2PD817 |
CY2PD817
Document #: 38-07574 Rev. **
Page 2 of 6
Pin Description
[1]
Pin
Name
I/O
I, PD
I, PU/PD
O
O
O
O
I, PD
I, PD
Type
LVPECL
LVPECL
LVPECL
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Description
2
3
6
7
23, 22
14, 15, 18, 19
12
9
PCLKI
PCLKI
PCLKO
PCLKO
QA[1,0]
QB[3:0]
CLRDIV
OE
LVPECL reference clock input
LVPECL reference clock input
LVPECL clock output
LVPECL clock output
Bank A, LVCMOS clock outputs
Bank B, LVCMOS clock outputs
Clear divider input. See functional
Table 1
Output enable/disable input. See functional
Table 1
2.5V power supply
[2]
Common ground
1, 5, 10, 16, 20, 24
4, 8, 11, 13, 17, 21
VDD
VSS
Supply
Supply
VDD
Ground
Table 1. Functional Table
Control
CLRDIV
Default
0
0
0
1
Bank A = ÷4, Bank B = ÷2
All outputs are enabled
Bank A = ÷1, Bank B = ÷1
All outputs are three-stated
OE
Absolute Maximum Conditions
Parameter
V
DD
V
DD
V
IN
Description
Condition
Min.
–0.5
2.375
–0.5
Max.
3.3
2.625
V
DD
+ 0.5
Unit
V
V
V
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
Functional
Relative to V
SS
, with or V
DD
applied
Relative to V
SS
LVCMOS outputs
LVPECL output
Functional
Ripple Frequency < 100 kHz
Non-functional
Functional
Functional
Functional
Functional
V
OUT
V
TT
DC Output Voltage
Output termination Voltage
–0.5
V
DD
+ 0.5
V
V
V
DD
/ 2
V
DD
– 2
LU
R
PS
T
S
T
A
T
J
JC
JA
ESD
H
Latch Up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body
Model)
Failure in Time
200
–
–65
0
–
–
–
2000
–
mA
mVp-p
°C
°C
°C
°C/W
°C/W
V
150
+150
+85
+150
42
105
–
FIT
Manufacturing test
10
ppm
Notes:
1.
2.
PU = Internal pull up, PD = Internal pull down.
A 0.1-uF bypass capacitor should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the trace.
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