- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379008 > CY2CC1910 (Cypress Semiconductor Corp.) .1UF 20% 25V CER. X7R PDF資料下載
參數(shù)資料
| 型號(hào)： | CY2CC1910 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | .1UF 20% 25V CER. X7R |
| 中文描述： | 1:10時(shí)鐘扇出緩沖器的輸出使能 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | CY2CC1910 |
COMLINK
SERIES
CY2CC1910
Document #: 38-07347 Rev. *B
Page 3 of 8
DC Electrical Characteristics
@ 1.8V (see
Figure 6
)
Parameter
V
DD
V
IH
V
IL
V
OH
V
OL
Description
Test Condition
[3]
Min.
1.71
Max.
1.89
4.3
Unit
V
V
V
V
V
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
0.65V
DD
[1.1]
–
0.3
V
DD
–
0.45[1.2]
0.35V
DD
[0.6]
I
OH
=
–
2 mA
I
OH
= 2 mA
0.45
Capacitance
Parameter
Description
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
2.5
6.5
Max.
Unit
pF
pF
C
IN
C
OUT
Input Capacitance
Output Capacitance
Power Supply Characteristics
(see
Figure 2
)
Parameter
I
CC
Description
Test Conditions
Min.
Typ.
Max.
50
Unit
uA
Delta I
CC
Quiescent Power
Supply Current
Dynamic Power Supply Current V
= Max.
(I
DD
@V
DD
= Max. and V
IN
= V
DD
)
–
(I
DD
@V
DD
= Max. and V
IN
= V
DD
–
0.6V)
I
CCD
Input toggling 50% Duty Cycle, Outputs Open
V
DD
= Max.
Input toggling 50% Duty Cycle, Outputs Open
fL = 40 MHZ
0.63
mA/
MHz
mA
I
C
Total Power Supply Current
25
High-frequency Parametrics
Parameter
Description
Test Conditions
Min. Typ. Max. Unit
D
J
Jitter, deterministic
50% duty cycle tW(50
–
50)
The
“
point to point load circuit
”
| Output Jitter
–
Input Jitter |
50% duty cycle tW(50
–
50)
Standard Load Circuit.
50% duty cycle tW(50
–
50)
The
“
point to point load circuit
”
The
“
point to point load circuit
”
V
IN
= 2.4V/0.0V
V
OUT
= 1.7V/0.7V
The
“
6-pF load circuit
”
V
IN
= 1.7V/0.0V
V
OUT
= 1.2V/0.4V
20% duty cycle tW(20
–
80)
The
“
point to point load circuit
”
V
IN
= 3.0V/0.0V
V
OUT
= 2.3V/0.4V
The
“
point to point load circuit
”
V
IN
= 3.0V/0.0V F = 100 MHz
V
OUT
= 2.0V/0.8V
The
“
point to point load circuit
”
V
IN
= 2.4V/0.0V F = 100 MHz
V
OUT
= 1.7V/0.7V
The
“
6-pF load circuit
”
V
IN
= 1.7V/0.0V
V
OUT
= 1.2V/0.4V
See
Figure 4
20
ps
F
max
3.3V
Maximum frequency
V
DD
= 3.3V
See
Figure 2
160
MHz
See
Figure 4
200
F
max
2.5V
Maximum frequency
V
DD
= 2.5V
See
Figure 4
200
MHz
F
max
1.8V
Maximum frequency
V
DD
= 1.8V
See
Figure 6
100
MHz
F
max(20)
Maximum frequency
V
DD
= 3.3V
See
Figure 4
250
MHz
t
W
3.3V
Minimum pulse
V
DD
= 3.3V
See
Figure 4
1
ns
t
W
2.5V
Minimum pulse
V
DD
= 2.5V
See
Figure 4
1
tW
1.8V
Minimum pulse
V
DD
= 1.8V
See
Figure 6
1
Note:
3.
Test Load conditions: 500 ohm to ground with approximately 6-pF total loading and 200-MHz maximum frequency.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2CC1910SC | 1:10 Clock Fanout Buffer with Output Enable |
| CY2CC1910SCT | 1:10 Clock Fanout Buffer with Output Enable |
| CY2CC1910SI | 1:10 Clock Fanout Buffer with Output Enable |
| CY2CC1910SIT | 1:10 Clock Fanout Buffer with Output Enable |
| CY2DP814SC | 1:4 Clock Fanout Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2CC1910OC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:10 Clock Fanout Buffer with Output Enable |
| CY2CC1910OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:10 Clock Fanout Buffer with Output Enable |
| CY2CC1910OI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:10 Clock Fanout Buffer with Output Enable |
| CY2CC1910OIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:10 Clock Fanout Buffer with Output Enable |
| CY2CC1910SC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:10 Clock Fanout Buffer with Output Enable |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。