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參數(shù)資料
| 型號： | CY29972AI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 3.3V, 125-MHz Multi-Output Zero Delay Buffer |
| 中文描述： | 125 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-52 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 70K |
| 代理商： | CY29972AI |
CY29972
Document #: 38-07290 Rev. *A
Page 5 of 8
Power Management
The individual output enable/freeze control of the CY29972
allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic
‘
0
’
state when the freeze control bits are activated. The serial
input register contains one programmable freeze enable bit for
12 of the 14 output clocks. The QC0 and FB_OUT outputs can
not be frozen with the serial port, this avoids any potential lock
up situation should an error occur in the loading of the serial
data. An output is frozen when a logic
‘
0
’
is programmed and
enabled when a logic
‘
1
’
is written. The enabling and freezing
of individual outputs is done in such a manner as to eliminate
the possibility of partial
“
runt
”
clocks.
The serial input register is programmed through the SDATA
input by writing a logic
‘
0
’
start bit followed by 12 NRZ freeze
enable bits. The period of each SDATA bit equals the period of
the free running SCLK signal. The SDATA is sampled on the
rising edge of SCLK.
Figure 2.
Notes:
3.
For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meet or exceed these specifi-
cations.
Larger values may cause this device to exhibit oscillator start-up problems.
4.
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Start
Bit
Table 3. Suggested Oscillator Crystal Parameters
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
T
C
Frequency Tolerance
±100
PPM
Note 3
T
S
Frequency Temperature
Stability
±100
PPM
(T
A
–
10 to +60
°
C)
[3]
T
A
Aging
5
PPM/Yr
(first 3 years @ 25
°
C)
[3]
The crystal
’
s rated load.
[3]
C
L
Load Capacitance
20
–
pF
R
ESR
Effective Series Resistance
(ESR)
40
80
Ohms
Note 44
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| CY29972AIT | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 200MHz to 480MHz 52-Pin TQFP T/R |
| CY29972AXI | 功能描述:鎖相環(huán) - PLL ZERO DELAY PLL SINGLE 200-480MHz RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29972AXIT | 功能描述:鎖相環(huán) - PLL 3.3V 125MHz IND RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29973 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz Multi-Output Zero Delay Buffer |
| CY29973_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz Multi-Output Zero Delay Buffer |
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