參數(shù)資料
型號： CY29972AI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： 3.3V, 125-MHz Multi-Output Zero Delay Buffer
中文描述： 125 MHz, OTHER CLOCK GENERATOR, PQFP52
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-52
文件頁數(shù)： 2/8頁
文件大小： 70K
代理商： CY29972AI
CY29972
Document #: 38-07290 Rev. *A
Page 2 of 8
Pin Description
[2]
Pin
11
12
9
10
Name
X
IN
X
OUT
T
CLK0
T
CLK1
QA(3:0)
QB(3:0)
QC(3:0)
FB_OUT
PWR
I/O
I
O
I
I
O
O
O
O
Type
Description
Oscillator Input
. Connect to a crystal.
Oscillator Output
. Connect to a crystal.
External Reference/Test Clock Input.
External Reference/Test Clock Input.
Clock Outputs
.
See
Table 2
for frequency selections.
Clock Outputs
. See
Table 2
for frequency selections.
Clock Outputs
. See
Table 2
for frequency selections.
Feedback Clock Output
. Connect to FB_IN for normal operation.
The divider ratio for this output is set by FB_SEL(0:2). See
Table 1
.
A bypass delay capacitor at this output will control Input Reference/
Output Banks phase relationships.
Synchronous Pulse Output
. This output is used for system
synchronization. The rising edge of the output pulse is in sync with
both the rising edges of QA (0:3) and QC(0:3) output clocks
regardless of the divider ratios selected.
Frequency Select Inputs
. These inputs select the divider ratio at
QA(0:3) outputs. See
Table 2
.
Frequency Select Inputs
. These inputs select the divider ratio at
QB(0:3) outputs. See
Table 2
.
Frequency Select Inputs
. These inputs select the divider ratio at
QC(0:3) outputs. See
Table 2
.
Feedback Select Inputs
. These inputs select the divide ratio at
FB_OUT output. See
Table 1.
VCO Divider Select Input
. When set low, the VCO output is
divided by 2. When set high, the divider is bypassed. See
Table 1
.
Feedback Clock Input
. Connect to FB_OUT for accessing the
PLL.
PLL Enable Input
. When asserted high, PLL is enabled. And when
low, PLL is bypassed.
Reference Select Input
. When high, the crystal oscillator is
selected. And when low, TCLK (0,1) is the reference clock.
TCLK Select Input
. When LOW, TCLK0 is selected and when high
TCLK1 is selected.
Master Reset/Output Enable Input
. When asserted low, resets all
of the internal flip-flops and also disables all of the outputs. When
pulled high, releases the internal flip-flops from reset and enables
all of the outputs.
Inverted Clock Input
. When set high, QC(2,3) outputs are
inverted. When set low, the inverter is bypassed.
Serial Clock Input
. Clocks data at SDATA into the internal register.
Serial Data Input
. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
PU
PU
44, 46, 48, 50
32, 34, 36, 38
16, 18, 21, 23
29
V
DDC
V
DDC
V
DDC
V
DDC
25
SYNC
V
DDC
O
42, 43
SELA(1,0)
I
PU
40, 41
SELB(1,0)
I
PU
19, 20
SELC(1,0)
I
PU
5, 26, 27
FB_SEL(2:0)
I
PU
52
VCO_SEL
I
PU
31
FB_IN
I
PU
6
PLL_EN
I
PU
7
REF_SEL
I
PU
8
TCLK_SEL
I
PU
2
MR#/OE
I
PU
14
INV_CLK
I
PU
3
4
S
CLK
S
DATA
I
I
PU
PU
17, 22, 28,
33,37, 45, 49
13
1, 15, 24, 30,
35, 39, 47, 51
V
DDC
3.3V power supply for output clock buffers.
V
DD
V
SS
3.3V power supply for PLL.
Common ground.
Note:
2.
A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power (< 0.2
”
). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
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