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參數(shù)資料
| 型號(hào)： | CY29972AI |
| 廠(chǎng)商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | 3.3V, 125-MHz Multi-Output Zero Delay Buffer |
| 中文描述： | 125 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-52 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 70K |
| 代理商： | CY29972AI |
CY29972
Document #: 38-07290 Rev. *A
Page 3 of 8
Description
The CY29972 has an integrated PLL that provides low skew
and low jitter clock outputs for high-performance micropro-
cessors. Three independent banks of four outputs and an
independent PLL feedback output (FB_OUT) provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the V
CO
is configured to
run between 200 MHz and 480 MHz. This allows a wide range
of output frequencies up to125 MHz.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input (FB_IN) is connected to the feedback output
(FB_OUT). The internal V
CO
is running at multiples of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select
inputs (refer to Frequency Table). The V
CO
frequency is then
divided to provide the required output frequencies. These
dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select
inputs (see
Table 3
below). For situations were the V
CO
needs
to run at relatively low frequencies and hence might not be
stable, assert VCO_SEL low to divide the VCO frequency by
2. This will maintain the desired output relationships but will
provide an enhanced PLL lock range.
The CY29972 is also capable of providing inverted output
clocks. When INV_CLK is asserted HIGH, QC2 and QC3
output clocks are inverted. These clocks could be used as
feedback outputs to the CY29972 or a second PLL device to
generate early or late clocks for a specific design. This
inversion does not affect the output to output skew.
Glitch-Free Output Frequency Transitions
Customarily, when output buffers have their internal counters
changed
“
on the fly,
”
their output clock periods will:
1. contain short or
“
runt
”
clock periods. These are clock cycles
in which the cycle(s) are shorter in period than either the
old or new frequencies to which the cycles are being tran-
sitioned.
2. contain stretched clock periods. These are clock cycles in
which the cycle(s) are longer in period than either the old
or new frequencies to which the cycles are being transi-
tioned.
This device specifically includes logic to guarantee that runt
and stretched clock pulses do not occur if the device logic
levels of any or all of the following pins changed
“
on the fly
”
while it is operating: SELA, SELB, SELC, and VCO_SEL.
SYNC Output
In situations where output frequency relationships are not
integer multiples of each other, the SYNC output provides a
signal for system synchronization. The CY29972 monitors the
relationship between the QA and QC output clocks. It provides
a LOW-going pulse, one period in duration, one period prior to
the coincident rising edges of the QA and QC outputs. The
duration and placement of the pulse depend on the higher of
the QA and QC output frequencies. The following timing
diagram illustrates various waveforms for the SYNC output.
Note that the SYNC output is defined for all possible combina-
tions of QA and QC outputs, even though under some relation-
ships the lower frequency clock could be used as a synchro-
Table 2.
VCO_SEL
SELA1
SELA0
QA
SELB1
SELB0
QB
SELC1
SELC0
QC
0
0
0
VCO/8
0
0
VCO/8
0
0
VCO/4
0
0
1
VCO/12
0
1
VCO/12
0
1
VCO/8
0
1
0
VCO/16
1
0
VCO/16
1
0
VCO/12
0
1
1
VCO/24
1
1
VCO/20
1
1
VCO/16
1
0
0
VCO/4
0
0
VCO/4
0
0
VCO/2
1
0
1
VCO/6
0
1
VCO/6
0
1
VCO/4
1
1
0
VCO/8
1
0
VCO/8
1
0
VCO/6
1
1
1
VCO/12
1
1
VCO/10
1
1
VCO/8
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY29972AIT | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 200MHz to 480MHz 52-Pin TQFP T/R |
| CY29972AXI | 功能描述:鎖相環(huán) - PLL ZERO DELAY PLL SINGLE 200-480MHz RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29972AXIT | 功能描述:鎖相環(huán) - PLL 3.3V 125MHz IND RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29973 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:3.3V 125-MHz Multi-Output Zero Delay Buffer |
| CY29973_08 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:3.3V 125-MHz Multi-Output Zero Delay Buffer |
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