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參數(shù)資料
| 型號(hào)： | CY292510 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 72K |
| 代理商： | CY292510 |
200-MHz, Ten-output Zero Delay Buffer/PLL
CY292510
Cypress Semiconductor Corporation
Document #: 38-07472 Rev. **
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised October 11, 2002
Features
Output frequency range: 25 MHz to 200 MHz
10 LVCMOS outputs
One feedback output
Output-to-output skew < 100 ps
Cycle-to cycle jitter < 100 ps
± 125-ps static phase error: 66 MHz to 166 MHz
Spread-Spectrum-compatible
Integrated series damping resistors specifically
designed for registered SDRAM DIMM applications –
JEDEC-JC42.5-compliant
Externally controllable output delay
Output enable/disable control
24-pin TSSOP package
Description
The CY292510 is a 3.3V zero delay buffer designed to
distribute high-speed clocks in PC, workstation, datacom,
telecom, and other high-performance applications. It is ideal
for use in SDRAM memory applications, and conforms to the
JEDEC JC40/JC42.5 specification supporting SDRAM DIMM
applications.
The CY292510 has one bank of outputs with output enable
control. Input-to-output skew can be adjusted by varying
load/delay on feedback path. When OE is low, clock outputs
are forced low. V
DDA
can be strapped low to force device into
test mode. See
Table 4
.
Table 1. Function Table
[1]
Note:
1.
See
Table 4
for additional logic configurations. REF is fixed frequency input.
OE
LOW
HIGH
1Y(0:9) Outputs
LOW
REF
FBOUT
REF
REF
Block Diagram
Pin Configuration
1
MUX
0
SEL
FBIN
REF
VDDA
1Y9
1Y8
1Y7
1Y6
1Y5
OE
1Y3
1Y4
1Y2
1Y1
1Y0
FBOUT
PLL
V
SSA
V
DD
1Y0
1Y1
1Y2
V
SS
V
SS
1Y3
1Y4
V
DD
OE
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
REF
V
DDA
V
DD
1Y9
1Y8
V
SS
V
SS
1Y7
1Y6
1Y5
V
DD
FBIN
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY29350 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 9-Output Clock Driver |
| CY29350_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver Nine Clock outputs: Drive up to 18 clock lines |
| CY29350AI | 制造商:Cypress Semiconductor 功能描述:PLL Clock Driver Single 32-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:2.5/3.3V,200MHZ,XTAL/LVCMOS INPUT,9 OUTPUT CLK GEN - Bulk |
| CY29350AIT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY29350AXI | 功能描述:鎖相環(huán) - PLL 200MHz 9-OP Clk Dvr 2.5/3.3volts RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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