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參數(shù)資料
| 型號(hào)： | CY29977 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 193K |
| 代理商： | CY29977 |
2.5V or 3.3V, 200-MHz
1:18 Clock Distribution Buffer
CY29940-1
Cypress Semiconductor Corporation
Document #: 38-07487 Rev. **
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 28, 2003
Features
200-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS/LVTTL-compatible inputs
18 clock outputs: drive up to 36 clock lines
150 ps max. output-to-output skew
23
output impedance
Dual or single supply operation:
—3.3V core and 3.3V outputs
—3.3V core and 2.5V outputs
—2.5V core and 2.5V outputs
Pin-compatible with MPC940L, MPC9109
Available in commercial and industrial temperature
ranges
32-pin TQFP package
Description
The CY29940-1 is a low-voltage 200-MHz clock distribution
buffer with the capability to select either a differential LVPECL-
or a LVCMOS/LVTTL-compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are
LVCMOS/LVTTL-compatible. The eighteen outputs are 2.5V
or 3.3V LVCMOS/LVTTL-compatible and can drive 50
series
or parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:36. Low
output-to-output skews make the CY29940-1 an ideal clock
distribution buffer for nested clock trees in the most
demanding of synchronous systems.
Block Diagram
Pin Configuration
PECL_CLK
PECL_CLK#
0
1
TCLK
TCLK_SEL
VDDC
18
Q0-Q17
VDD
CY29940-1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
Q
Q
V
Q
Q
Q
V
24
23
22
21
20
19
18
17
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
25
26
27
28
29
30
31
32
Q
Q
Q
V
Q
Q
Q
V
VSS
VSS
TCLK
TCLK_SEL
PECL_CLK
PECL_CLK#
VDD
VDDC
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