
CY28508
........................ Document #: 38-07534 Rev. *F Page 2 of 13
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1. The block write and block read
sponding byte write and byte read protocol. The Byte Count
value returned is 09h.
The slave receiver address is either D2 or D4, depending on
the state of the ADDRSEL pin.
Note:
1. Throughout this document logic 0 and logic 1 state signals are referenced. As a clarification it should be understood that 1 = high and 0 = low voltage levels. These
levels are defined in the DC Electrical Specifications of this data sheet.
Pin
Name
Type
Power
Description
1REF
O
VDDX
Reference Clock. 3.3V 14.318-Mz clock output.
3XIN
I
VDDX
Crystal Connection or External Reference Frequency Input. This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection
or as an external reference frequency input.
4XOUT
O
VDDX
Crystal Connection. Connection for an external 14.318-MHz crystal output.
27, 23, 19
CPUT[0:2]
O
VDDQ CPUT Clock Outputs: Differential True CPU clock outputs.
26, 22, 18
CPUC[0:2]
O
VDDQ CPUC Clock Outputs: Differential Complementary CPU clock outputs.
6
FSEL
I, PU
250K
VDD
3.3V LVTTL input for CPU frequency selection.
0 = M&N register set 0, 1 = M&N register set 1.
11
SDATA
I/O
VDD
I2C-compatible SDATA.
12
SCLK
I
VDD
I2C-compatible SCLOCK.
14
CPU_STOP#
I, PU
250K
VDD
CPU stop. 1 = CPUT/C running, 0 = CPUT stopped synchronously low and
CPUC stopped synchronously high. REF remains running.
9
ADDRSEL
I, PD
250K
VDD
I2C address selection. 0 = D2, 1 = D4.
10
LOCK
Open
Drain
VDD
It is recommended that an external 10K
resistor is connected to this pin.
With this resistor, 1 = Signifies the VCO has locked onto the target frequency.
0 = Not locked to the designated M&N register pair target frequency.
16
VDDA
PWR
3.3V power supply for analog PLL.
15
VSSA
GND
Ground for analog PLL.
28, 24, 20
VDDQ
PWR
2.5V power supply for output buffers.
25, 21, 17
VSSQ
GND
Ground for output buffers.
2
VDDX
PWR
3.3V power supply for oscillator.
5
VSSX
GND
Ground for oscillator.
7
VDDC
PWR
3.3V power supply for core.
8
VSSC
GND
Ground for core.
13
VDD
PWR
3.3V power supply.