參數(shù)資料
型號(hào): CY28442ZXC-2T
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 4/19頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK ALVISO PENTM 56TSSOP
標(biāo)準(zhǔn)包裝: 2,000
類型: 時(shí)鐘/頻率發(fā)生器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: LVTTL,晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 3:20
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 200MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
其它名稱: SLCY28442ZXC-2T
CY28442-2
..................... Document #: 38-07691 Rev. *B Page 12 of 19
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
CPU_STP#
CPUT
CPUC
CPUT Internal
Tdrive_CPU_STP#,10nS>200mV
CPUC Internal
Figure 7. CPU_STP# Deassertion Waveform
DOT96C
DOT96T
CPUC(Stoppable)
CPUT(Stoppable)
CPUC(Free Running
CPUT(Free Running
PD
1.8mS
CPU_STOP#
Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven
DOT96C
DOT96T
CPUC(Stoppable)
CPUT(Stoppable)
CPUC(Free Running)
CPUT(Free Running)
PD
1.8mS
CPU_STOP#
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY28442ZXCT 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器,PLL,頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器,零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG
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