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參數(shù)資料
| 型號(hào)： | CY28442ZXC-2T |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 2/19頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLOCK ALVISO PENTM 56TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:20 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SLCY28442ZXC-2T |
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CY28442-2
..................... Document #: 38-07691 Rev. *B Page 10 of 19
CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW)
All differential outputs that were stopped are to resume normal
operation in a glitch-free manner. The maximum latency from
the assertion to active outputs is between 2 and 6 SRC clock
periods (2 clocks are shown) with all SRC outputs resuming
simultaneously. All stopped SRC outputs must be driven high
within 10 ns of CLKREQ#[1:0] deassertion to a voltage greater
than 200 mV.
CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH)
The impact of deasserting the CLKREQ#[A:B] pins is that all
SRC outputs that are set in the control registers to stoppable
via deassertion of CLKREQ#[A:B] are to be stopped after their
next transition. The final state of all stopped DIF signals is
LOW, both SRCT clock and SRCC clock outputs will not be
driven.
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual-function pin. During
initial power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled LOW by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted HIGH, all clocks need to be
driven to a LOW value and held prior to turning off the VCOs
and the crystal oscillator.
PD (Power-down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
high or tri-stated (depending on the state of the control register
drive mode bit) on the next diff clock# HIGH-to-LOW transition
within 4 clock periods. When the SMBus PD drive mode bit
corresponding to the differential (CPU, SRC, and DOT) clock
output of interest is programmed to ‘0’, the clock output are
held with “Diff clock” pin driven HIGH at 2 x Iref, and “Diff
clock#” tri-state. If the control register PD drive mode bit corre-
sponding to the output of interest is programmed to “1”, then
both the “Diff clock” and the “Diff clock#” are tri-state. Note the
example below shows CPUT = 133 MHz and PD drive mode
= ‘1’ for all differential outputs. This diagram and description is
applicable to valid CPU frequencies 100, 133, 166, 200, 266,
333, and 400 MHz. In the event that PD mode is desired as
the initial power-on state, PD must be asserted HIGH in less
than 10
s after asserting Vtt_PwrGd#.
Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform
SRCT(stoppable)
SRCC(free running)
SRCT(free running)
CLKREQ#X
Figure 4. Power-down Assertion Timing Waveform
PD
USB, 48MHz
DOT96T
DOT96C
SRCT 100MHz
SRCC 100MHz
CPUT, 133MHz
PCI, 33 MHz
REF
CPUC, 133MHz
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| CY28442ZXCT | 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| CY28443 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel㈢ Calistoga Chipset |
| CY28443-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel㈢ Calistoga Chipset |
| CY28443-3 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel㈢ Calistoga Chipset |
| CY28443OXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel㈢ Calistoga Chipset |
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