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參數(shù)資料
| 型號(hào)： | CY28442ZXC-2T |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 12/19頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK ALVISO PENTM 56TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:20 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SLCY28442ZXC-2T |
CY28442-2
....................... Document #: 38-07691 Rev. *B Page 2 of 19
Pin Definitions
Pin No.
Name
Type
Description
1
VDD_REF
PWR
3.3V power supply for output
2
VSS_REF
GND
Ground for outputs.
33,32
CLKREQA#/SRCT6,
CLKREQB#,SRCC6
I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW) or 100-MHz
Serial Reference Clock.
Selectable through CLKREQA# defaults to enable/disable SRCT/C4, CLKREQB#
defaults to enable/disable SRCT/C5. Assignment can be changed via SMBUS
register Byte 8.
7
VDD_PCI
PWR
3.3V power supply for outputs.
6
VSS_PCI
GND
Ground for outputs.
3,4,5
PCI
O, SE 33 MHz clock
8
ITP_EN/PCIF0
I/O, SE 3.3V LVTTL input to enable SRC7 or CPU2_ITP/33-MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
9
PCIF1/96_100_SEL
I/O,
PD,SE
33 MHz clock/3.3V-tolerant input for 96_100M frequency selection
(sampled on the VTT_PWRGD# assertion).
1 = 100 MHz, 0 = 96 MHz
10
VTT_PWRGD#/PD
I, PU
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C and ITP_EN, 96MSS_SRC_SEL inputs, SEL_CLKREQ. After
VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for
asserting power-down (active HIGH).
11
VDD_48
PWR
3.3V power supply for outputs.
12
FS_A/48_M0
I/O
3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
13
VSS_48
GND
Ground for outputs.
14,15
DOT96T, DOT96C
O, DIF Fixed 96 MHz clock output.
16
FS_B/TEST_MODE
I
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state
when in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
17,18
96_100_SSC
O,DIF Differential 96 /100 MHz SS clock for flat-panel display
19,20,22,23,
24,25,30,31
SRCT/C
O, DIF 100 MHz Differential serial reference clocks.
21,28
VDD_SRC
PWR
3.3V power supply for outputs.
34
VDD_SRC_ITP
PWR
3.3V power supply for outputs.
26,27
SRC4_SATAT,
SRC4_SATAC
O, DIF Differential serial reference clock. Recommended output for SATA.
29
VSS_SRC
GND
Ground for outputs.
36,35
CPUT2_ITP/SRCT7,
CPUC2_ITP/SRCC7
O, DIF Selectable differential CPU or SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
37
VDDA
PWR
3.3V power supply for PLL.
38
VSSA
GND
Ground for PLL.
39
IREF
I
A precision resistor is attached to this pin, which is connected to the internal
current reference.
42
VDD_CPU
PWR
3.3V power supply for outputs.
44,43,41,40
CPUT/C
O, DIF Differential CPU clock outputs.
45
VSS_CPU
GND
Ground for outputs.
46
SCLK
I
SMBus-compatible SCLOCK.
47
SDATA
I/O
SMBus-compatible SDATA.
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| CY28442ZXCT | 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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