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參數資料
| 型號： | CY28441 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Clock Generator for Intel Alviso Chipset |
| 中文描述： | 時鐘發(fā)生器英特爾Alviso芯片組 |
| 文件頁數： | 7/20頁 |
| 文件大?。?/td> | 261K |
| 代理商： | CY28441 |
CY28441
Document #: 38-07679 Rev. **
Page 7 of 20
6
0
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Hi-Z mode,
Reserved, Set = 0
REF Output Drive Strength
0 = 1X, 1 = 2X
SW PCI_STP Function
0=SW PCI_STP assert, 1= SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
FS_C Reflects the value of the FS_C pin sampled on power up
0 = FS_C was low during VTT_PWRGD# assertion
FS_B Reflects the value of the FS_B pin sampled on power up
0 = FS_B was low during VTT_PWRGD# assertion
FS_A Reflects the value of the FS_A pin sampled on power up
0 = FS_A was low during VTT_PWRGD# assertion
5
4
0
1
Reserved
REF
3
1
PCIF, SRC, PCI
2
Externally
selected
Externally
selected
Externally
selected
CPUT/C
1
CPUT/C
0
CPUT/C
Byte 6: Control Register 6
(continued)
Bit
@Pup
Name
Description
Byte 7: Vendor ID
Bit
@Pup
0
0
0
0
1
0
0
0
Name
Description
7
6
5
4
3
2
1
0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
BYTE 8: CLKREQ Control Register
Bit
@Pup
0
1
Name
Description
7
6
Reserved
CLKREQ#B
Reserved
SRC[T/C]5 CLKREQ#B control
1 = SRC[T/C]5 stoppable by CLKREQ#B pin
0 = SRC[T/C]5 not controlled by CLKREQ#B pin
SRC[T/C]3 CLKREQ#B control
1 = SRC[T/C]3 stoppable by CLKREQ#B pin
0 = SRC[T/C]3 not controlled by CLKREQ#B pin
SRC[T/C]1 CLKREQ#B control
1 = SRC[T/C]1 stoppable by CLKREQ#B pin
0 = SRC[T/C]1 not controlled by CLKREQ#B pin
Reserved
SRC[T/C]4 CLKREQ#A control
1 = SRC[T/C]4 stoppable by CLKREQ#A pin
0 = SRC[T/C]4 not controlled by CLKREQ#A pin
SRC[T/C]2 CLKREQ#A control
1 = SRC[T/C]2 stoppable by CLKREQ#A pin
0 = SRC[T/C]2 not controlled by CLKREQ#A pin
SRC[T/C]0 CLKREQ#A control
1 = SRC[T/C]0 stoppable by CLKREQ#A pin
0 = SRC[T/C]0 not controlled by CLKREQ#A pin
5
0
CLKREQ#B
4
0
CLKREQ#B
3
2
0
1
Reserved
CLKREQ#A
1
0
CLKREQ#A
0
0
CLKREQ#A
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY28441OXC | 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| CY28441ZXC | 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| CY28441ZXCT | 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| CY28442 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel Alviso Chipset |
| CY28442-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel Alviso Chipset |
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