參數(shù)資料
型號(hào)： CY28441
廠商： Cypress Semiconductor Corp.
英文描述： Clock Generator for Intel Alviso Chipset
中文描述： 時(shí)鐘發(fā)生器英特爾Alviso芯片組
文件頁(yè)數(shù)： 6/20頁(yè)
文件大小： 261K
代理商： CY28441
CY28441
Document #: 38-07679 Rev. **
Page 6 of 20
4
0
SRC4
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]0 with assertion of PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3
0
SRC3
2
0
SRC2
1
0
SRC1
0
0
SRC0
Byte 3: Control Register 3
(continued)
Bit
@Pup
Name
Description
Byte 4: Control Register 4
Bit
7
6
@Pup
0
0
Name
Reserved
DOT96T/C
Description
Reserved, Set = 0
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Hi-Z
Reserved, Set = 0
Allow control of PCIF1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of PCIF0 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
5
4
0
0
Reserved
PCIF1
3
0
PCIF0
2
1
CPU[T/C]2
1
1
CPU[T/C]1
0
1
CPU[T/C]0
Byte 5: Control Register 5
Bit
7
@Pup
0
Name
Description
SRC[T/C][7:0]
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted,1 = Hi-Z when PCI_STP# asserted
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
6
0
CPU[T/C]2
5
0
CPU[T/C]1
4
0
CPU[T/C]0
3
0
SRC[T/C][7:0]
2
0
CPU[T/C]2
1
0
CPU[T/C]1
0
0
CPU[T/C]0
Byte 6: Control Register 6
Bit
7
@Pup
0
Name
Description
REF/N or Hi-Z Select
0 = Hi-Z, 1 = REF/N Clock
相關(guān)PDF資料
PDF描述
CY28441ZXC Clock Generator for Intel Alviso Chipset
CY28441ZXCT Clock Generator for Intel Alviso Chipset
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