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參數(shù)資料
| 型號： | CY28411ZXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 11/18頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CK410M ALVISO 56TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:19 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 133MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SLCY28411ZXCT |
CY28411
........................ Document #: 38-07594 Rev. *B Page 2 of 18
Pin Definitions
Pin No.
Name
Type
Description
54
CPU_STP#
I, PU
3.3V LVTTL input for CPU_STP# active low.
44,43,41,40
CPUT/C
O, DIF Differential CPU clock outputs.
36,35
CPUT2_ITP/SRCT7,
CPUC2_ITP/SRCC7
O, DIF Selectable differential CPU or SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
14,15
DOT96T, DOT96C
O, DIF Fixed 96 MHz clock output.
12
FS_A/USB_48
I/O, SE 3.3V-tolerant input for CPU frequency selection/fixed 48 MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
16
FS_B/TEST_MODE
I
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when
in test mode
0 = Hi-Z, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
53
FS_C/TEST_SEL
I
3.3V-tolerant input for CPU frequency selection. Selects test mode if pulled
to VIMFS_C when VTT_PWRGD# is asserted low.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifi-
cations.
39
IREF
I
A precision resistor is attached to this pin, which is connected to the internal
current reference.
56,3,4,5
PCI
O, SE 33 MHz clocks.
55
PCI_STP#
I, PU
3.3V LVTTL input for PCI_STP# active low.
8
PCIF0/ITP_EN
I/O, SE 33 MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
9
PCIF1
O, SE 33 MHz clocks.
52
REF
O, SE Reference clock. 3.3V 14.318-MHz clock output.
46
SCLK
I
SMBus-compatible SCLOCK.
47
SDATA
I/O
SMBus-compatible SDATA.
26,27
SRC4_SATAT,
SRC4_SATAC
O, DIF Differential serial reference clock. Recommended output for SATA.
24,25,22,23,
19,20,17,18,
33,32,31,30
SRCT/C
O, DIF Differential serial reference clocks.
11
VDD_48
PWR
3.3V power supply for outputs.
42
VDD_CPU
PWR
3.3V power supply for outputs.
1,7
VDD_PCI
PWR
3.3V power supply for outputs.
48
VDD_REF
PWR
3.3V power supply for outputs.
21,28,34
VDD_SRC
PWR
3.3V power supply for outputs.
37
VDDA
PWR
3.3V power supply for PLL.
13
VSS_48
GND
Ground for outputs.
45
VSS_CPU
GND
Ground for outputs.
2,6
VSS_PCI
GND
Ground for outputs.
51
VSS_REF
GND
Ground for outputs.
29
VSS_SRC
GND
Ground for outputs.
38
VSSA
GND
Ground for PLL.
10
VTT_PWRGD#/PD
I, PU
3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,
FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD#
(active low) assertion, this pin becomes a real-time input for asserting power
down (active high).
50
XIN
I
14.318 MHz crystal input.
49
XOUT
O, SE 14.318 MHz crystal output.
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