參數(shù)資料
型號(hào)： CY284108ZXCT
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 16/16頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK SERV CK410B 56TSSOP
標(biāo)準(zhǔn)包裝： 2,000
類型： 時(shí)鐘/頻率發(fā)生器
PLL： 是
主要目的： Intel CPU 服務(wù)器
輸入： 晶體
輸出： HCSL，LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:19
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 400MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 56-TFSOP（0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 56-TSSOP
包裝： 帶卷 (TR)
CY284108
........................ Document #: 38-07713 Rev. *B Page 9 of 16
PD (Power-down) Assertion
When PD is sampled high by two consecutive rising edges of
CPUC, all single-ended outputs will be held low on their next
high to low transition and differential clocks must held high or
tri-stated (depending on the state of the control register drive
mode bit) on the next diff clock# high to low transition within 4
clock periods. When the SMBus PD drive mode bit corre-
sponding to the differential (CPU and SRC) clock output of
interest is programmed to ‘0’, the clock outputs are held with
“Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tri-state.
If the control register PD drive mode bit corresponding to the
output of interest is programmed to “1”, then both the “Diff
clock” and the “Diff clock#” are tri-state. Note that Figure 4
shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differ-
ential outputs. This diagram and description is applicable to
valid CPU frequencies 100, 133, 166, 200, 266, 333, and
400 MHz. In the event that PD mode is desired as the initial
power-on state, PD must be asserted high in less than 10
s
after asserting Vtt_PwrGd#.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300
s of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Figure 5 is an example showing the relationship of
clocks coming up.
PD
USB, 48 MHz
SRCT 100 MHz
SRCC 100 MHz
CPUT, 133 MHz
PCI, 33 MHz
REF
CPUC, 133 MHz
Figure 4. Power-down Assertion Timing Waveform
PD
CPUC, 133 MHz
CPUT, 133 MHz
SRCC 100 MHz
USB, 48 MHz
SRCT 100 MHz
Tstable
<1.8 ms
PCI, 33 MHz
REF
Tdrive_PWRDN#
<300
s, >200 mV
Figure 5. Power-down Deassertion Timing Waveform
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