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參數(shù)資料
| 型號： | CY284108ZXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SERV CK410B 56TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:19 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
CY284108
........................ Document #: 38-07713 Rev. *B Page 8 of 16
The CY284108 requires a parallel resonance crystal. Substi-
tuting a series resonance crystal will cause the CY284108 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure shows a typical crystal configuration using the two trim
capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It is a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Figure 2.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual-function pin. During
initial power up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled low by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted high, drive all clocks to a low
value and hold prior to turning off the VCOs and the crystal
oscillator.
Table 5. Crystal Recommendations
Frequency
(Fund)
Cut
Loading
Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
Figure 1. Crystal Capacitive Clarification
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8 pF
Trim
33 pF
Pin
3 to 6p
Figure 3. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
()
1
=
CLe
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| CY28410OXC-2T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SysClk Intel Lakeprt & Grantsdale Chipset RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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