參數(shù)資料
型號: CY28405OC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: CK409-Compliant Clock Synthesizer
中文描述: 200.9 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: SSOP-48
文件頁數(shù): 16/19頁
文件大?。?/td> 259K
代理商: CY28405OC
CY28405
Document #: 38-07512 Rev. *B
Page 16 of 19
T
LOW
T
R
/ T
F
PCIF and PCI Low Time
PCIF and PCI Rise and Fall Times
Measurement at 0.4V
Measured between 0.4V and
2.4V
12.0
ns
0.5
2.0
ns
T
SKEW
T
CCJ
DOT
T
DC
T
PERIOD
T
HIGH
T
LOW
T
R
/ T
F
Any PCI Clock to Any PCI Clock Skew Measurement at 1.5V
PCIF and PCI Cycle to Cycle Jitter
500
250
ps
ps
Measurement at 1.5V
Duty Cycle
Period
DOT High Time
DOT Low Time
Rise and Fall Times
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2.4V
Measurement at 0.4V
Measured between 0.4V and
2.4V
10-
μ
s period
45
55
%
ns
ns
ns
20.8257
8.994
8.794
20.8340
10.486
10.386
0.5
1.0
ns
T
CCJ
USB
T
DC
T
PERIOD
T
HIGH
T
LOW
T
R
/ T
F
Cycle to Cycle Jitter
350
ps
Duty Cycle
Period
USB High Time
USB Low Time
Rise and Fall Times
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2.4V
Measurement at 0.4V
Measured between 0.4V and
2.4V
125-
μ
s period
45
55
%
ns
ns
ns
20.8257
8.094
7.694
20.8340
10.036
9.836
1.0
2.0
ns
T
CCJ
REF
T
DC
T
PERIOD
T
R
/ T
F
Cycle to Cycle Jitter
350
ps
REF Duty Cycle
REF Period
REF Rise and Fall Times
Measurement at 1.5V
Measurement at 1.5V
Measured between 0.4V and
2.4V
Measurement at 1.5V
45
55
%
ns
69.827
69.855
1.0
4.0
V/ns
T
CCJ
ENABLE/DISABLE and SET-UP
T
STABLE
T
SS
T
SH
REF Cycle to Cycle Jitter
1000
ps
All Clock Stabilization from Power-up
Stopclock Set-up Time
Stopclock Hold Time
1.5
ms
ns
ns
10.0
0
Table 7. Group Timing Relationship and Tolerances
Group
3V66 to PCI
Conditions
3V66 Leads PCI
Offset
Min.
1.5 ns
Max.
3.5 ns
Table 8. USB to DOT Phase Offset
Parameter
DOT Skew
USB Skew
VCH SKew
Typical
180°
Value
0.0 ns
0.0 ns
0.0 ns
Tolerance
1000 ps
1000 ps
1000 ps
AC Electrical Specifications
(continued)
Parameter
Description
Conditions
Min.
Max.
Unit
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