參數(shù)資料
型號(hào): CY28405OC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: CK409-Compliant Clock Synthesizer
中文描述: 200.9 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: SSOP-48
文件頁數(shù): 10/19頁
文件大?。?/td> 259K
代理商: CY28405OC
CY28405
Document #: 38-07512 Rev. *B
Page 10 of 19
Dial-a-Frequency Programming
When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:
Fcpu = G * N/M
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
“G” stands for the PLL Gear Constant, which is determined by
the programmed value of FS[E:A] or SEL[4:0]. The value is
listed in
Table 1
.
The ratio of N and M need to be greater than “1” [N/M> 1].
The following table lists set of N and M values for different
frequency output ranges. This example use a fixed value for
the M-Value Register and select the CPU output frequency by
changing the value of the N-Value Register.
Crystal Recommendations
The CY28405 requires a
Parallel Resonance Crystal
.
Substituting a series resonance crystal will cause the
CY28405 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1
shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is
not true
.
4
3
2
1
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Pro_Freq_EN
Reserved, Set = 0
Reserved, Set = 0
Reserved, Set = 0
Reserved, Set = 0
Programmable output frequencies enabled
0 = Disabled, 1 = Enabled
Byte 14: Control Register 14
(continued)
Bit
@Pup
Name
Description
Table 5. Examples of N and M Value for Different CPU
Frequency Range
Frequency
Ranges
100 –125
126 – 166 32005345.76
167 – 200 48008018.65
Gear
Constants
24004009.32
Fixed Value
for M-Value
Register
48
48
48
Range of N-Value
Register for
Different CPU
Frequency
200 – 250
189 – 249
167 – 200
Table 6. Crystal Recommendations
Frequency
(Fund)
14.31818 MHz
Cut
Loading
Load Cap
Drive
(max.)
0.1 mW
Shunt Cap
(max.)
5 pF
Motional
(max.)
0.016 pF
Tolerance
(max.)
50 ppm
Stability
(max.)
50 ppm
Aging
(max.)
5 ppm
AT
Parallel
20 pF
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