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參數(shù)資料
| 型號： | CY28400OCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100-MHz Differential Buffer for PCI Express and SATA |
| 中文描述： | 28400 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 5.30 MM, SSOP-28 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 245K |
| 代理商： | CY28400OCT |
CY28400
Document #: 38-07591 Rev. **
Page 9 of 14
SRC_DIV2# Deassertion
The impact of writing a ‘0’ to the SRC_DIV/2 register bit is all
DIF outputs will transition cleanly in a glitch-free manner from
divide by 2 mode to normal (output frequency is equal to the
input frequency) operation within 2–6 DIF clock periods.
PLL/BYPASS# Clarification
The PLL/Bypass# input is used to select between bypass
mode (no PLL) and PLL mode. In bypass mode, the input clock
is passed directly to the output stage resulting in 50ps additive
jitter (50 ps + input jitter) on DIF outputs. In the case of PLL
mode, the input clock is pass through a PLL to reduce high
frequency jitter. The BYPASS# mode may be selected in two
ways, via writing a ‘0’ to SMBus register bit or by asserting the
PLL/BYPASS# pin low. In both methods, if the SMBus register
bit has been written low or PLL/BYPASS# pin is low or both,
the device will be configure for BYPASS operation.
HIGH_BW# Clarification
The HIGH_BW# input is used to set the PLL bandwidth. This
mode is intended to minimize PLL peaking when two or more
buffers are cascaded by staggering device bandwidths. The
PLL low bandwidth mode may be selected in two ways, via
writing a ‘0’ to SMBus register bit or by asserting the
HIGH_BW# pin is low or both, the device will be configured for
low bandwidth operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28401 | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28401OC | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28401OCT | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28405 | CK409-Compliant Clock Synthesizer |
| CY28405OXCT | CK409-Compliant Clock Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28400OXC | 功能描述:時鐘緩沖器 100 MHz Diff Buffer PCI Express & SATA RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OXC-2 | 功能描述:時鐘緩沖器 PCIe buffer 1in 4out RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OXC-2T | 功能描述:時鐘緩沖器 PCIe buffer 1in 4out RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OXCT | 功能描述:時鐘緩沖器 100 MHz Diff Buffer PCI Express & SATA RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OXI-2 | 功能描述:時鐘緩沖器 PCIe buffer 1in 4out RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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