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參數(shù)資料
| 型號(hào)： | CY28400OCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 100-MHz Differential Buffer for PCI Express and SATA |
| 中文描述： | 28400 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 5.30 MM, SSOP-28 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 245K |
| 代理商： | CY28400OCT |
CY28400
Document #: 38-07591 Rev. **
Page 5 of 14
PWRDWN# Clarification
[1]
The PWRDWN# pin is used to shut off all clocks cleanly and
instruct the device to evoke power savings mode. Additionally,
PWRDWN# should be asserted prior to shutting off the input
clock or power to ensure all clocks shut down in a glitch-free
manner. PWRDWN# is an asynchronous active low input. This
signal is synchronized internal to the device prior to powering
down the clock buffer. PWRDWN# is an asynchronous input
for powering up the system. When PWRDWN# is asserted
low, all clocks will be held high or three-stated (depending on
the state of the control register drive mode and OE bits) prior
to turning off the VCO. All clocks will start and stop without any
abnormal behavior and must meet all AC and DC parameters.
This means no glitches, frequency shifting or amplitude abnor-
malities among others.
PWRDWN#—Assertion
When PWRDWN# is sampled low by two consecutive rising
edges of DIFC, all DIFT outputs will be held high or
three-stated (depending on the state of the control register
drive mode and OE bits) on the next DIFC high to low
transition. When the SMBus power-down drive mode bit is
programmed to ‘0’, all clock outputs will be held with the DIFT
pin driven high at 2 x Iref and DIFC three-state. However, if the
control register PWRDWN# drive mode bit is programmed to
‘1’, then both DIFT and the DIFC are three-stated.
Note:
1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN# is an undefined mode and not recommended. Operation in this mode may result in glitches
excessive frequency shifting.
Byte 4: Vendor ID Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
0
0
0
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Byte 5: Control Register 5
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWRDWN#
DIFC
DIFT
Figure 1. PWRDWN# Assertion Diagram
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PDF描述 |
|---|---|
| CY28401 | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28401OC | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28401OCT | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28405 | CK409-Compliant Clock Synthesizer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28400OXC | 功能描述:時(shí)鐘緩沖器 100 MHz Diff Buffer PCI Express & SATA RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OXC-2 | 功能描述:時(shí)鐘緩沖器 PCIe buffer 1in 4out RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OXC-2T | 功能描述:時(shí)鐘緩沖器 PCIe buffer 1in 4out RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OXCT | 功能描述:時(shí)鐘緩沖器 100 MHz Diff Buffer PCI Express & SATA RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OXI-2 | 功能描述:時(shí)鐘緩沖器 PCIe buffer 1in 4out RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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