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參數(shù)資料
| 型號(hào)： | CY28400 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 100-MHz Differential Buffer for PCI Express and SATA |
| 中文描述： | 100 MHz的差分緩沖器，用于PCI Express和SATA |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 245K |
| 代理商： | CY28400 |
CY28400
Document #: 38-07591 Rev. **
Page 7 of 14
SRC_STOP# Clarification
The SRC_STOP# signal is an active low input used for clean
stopping and starting the DIF outputs (valid clock must be
present on SRCT_IN). The SRC_STOP# signal is a
de-bounced signal in that it’s state must remain unchanged
during two consecutive rising edges of DIFC to be recognized
as a valid assertion or deassertion. (The assertion and
deassertion of this signal is absolutely asynchronous).
SRC_STOP# Assertion
The impact of asserting the SRC_STOP# pin is all DIF outputs
that are set in the control registers to stoppable via assertion
of SRC_STOP# are stopped after their next transition. When
the control register SRC_STOP# three-state bit is
programmed to ‘0’, the final state of all stopped DIFT/C signals
is DIFT clock = High and DIFC = Low. There is to be no change
to the output drive current values, DIFT will be driven high with
a current value equal 6 x Iref, and DIFC will not be driven.
When the control register SRC_STOP# three-state bit is
programmed to ‘1’, the final state of all stopped DIF signals is
low, both DIFT clock and DIFC clock outputs will not be driven.
SRC_STOP# Deassertion
All differential outputs that were stopped will resume normal
operation in a glitch-free manner. The maximum latency from
the deassertion to active outputs is between 2–6 DIFT/C clock
periods (two clocks are shown) with all DIFT/C outputs
resuming simultaneously. If the control register three-state bit
is programmed to ‘1’ (three-state), then all stopped DIFT
outputs will be driven high within 10 ns of SRC_STOP#
deassertion to a voltage greater than 200 mV.
Note:
4. In the case where OE is asserted high, the output will always be three-stated regardless of SRC_STOP# drive mode register bit state.
Table 5. SRC_STOP# Functionality
[4]
SRC_STOP#
1
0
DIFT
Normal
DIFC
Normal
Low
Iref * 6 or Float
DIFC (Stoppable)
DIFT (Stoppable)
DIFC(Free Running
DIFT(Free Running
PWRDWN#
1mS
SRC_STOP#
Figure 4. SRC_STOP# = Driven, PWRDWN# = Driven
DIFC (Stoppable)
DIFC(Free Running
PWRDWN#
1mS
SRC_STOP#
DIFT (Stoppable)
DIFT(Free Running
Figure 5. SRC_STOP# =Driven, PWRDWN# = Three-state
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28400OC | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28400OCT | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28401 | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28401OC | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28401OCT | 100-MHz Differential Buffer for PCI Express and SATA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28400_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Differential Buffer for PCI Express and SATA |
| CY28400-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Differential Buffer for PCI Express and SATA |
| CY28400OC | 功能描述:時(shí)鐘緩沖器 100 MHz Diff Buffer PCI Express & SATA RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OCT | 功能描述:時(shí)鐘緩沖器 100 MHz Diff Buffer PCI Express & SATA RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OXC | 功能描述:時(shí)鐘緩沖器 100 MHz Diff Buffer PCI Express & SATA RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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