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參數(shù)資料
| 型號： | CY28400 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 100-MHz Differential Buffer for PCI Express and SATA |
| 中文描述： | 100 MHz的差分緩沖器，用于PCI Express和SATA |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 245K |
| 代理商： | CY28400 |
CY28400
Document #: 38-07591 Rev. **
Page 6 of 14
PWRDWN#—Deassertion
The power-up latency is less than 1ms. This is the time from
the deassertion of the PWRDWN# pin or the ramping of the
power supply or the time from valid SRC_IN input clocks until
the time that stable clocks are output from the buffer chip (PLL
locked). If the control register PWRDWN# three-state bit is
programmed to ‘1’, all differential outputs will be driven high in
less than 300
μ
S of PWRDWN# deassertion to a voltage
greater than 200 mV.
Notes:
2. The total power up latency from power on to all outputs active is less than 1 ms (assuming a valid clock is present on SRC_IN input).
3. If power is valid and PWRDWN# is deasserted but no input clocks are present on the SRC_IN input, DIF clocks will remain disabled. Only after valid input clocks
are detected, valid power, PWRDWN# deasserted with the PLL locked and stable are the DIF outputs enabled.
Table 4. Buffer Power-Up State Machine
State
0
1
2
[3]
3
[2]
Description
3.3V Buffer power off
After 3.3V supply is detected to rise above 1.8V–2.0V, the buffer enters state 1 and initiates a 0.2-ms–0.3-ms delay
Buffer
waits for a valid clock on the SRC_IN input
and PWRDWN# deassertion
Once the PLL is locked to the SRC_IN input clock, the buffer enters state 3 and enables outputs for normal operation
DIFC
DIFT
Tstable
<1mS
PWRDWN#
Tdrive_Pwrdwn#
<300uS, >200mV
Figure 2. PWRDWN# Deassertion Diagram
S2
Wait for Input
Clock &
PWRDWN# De-
assertion
PWRDWN# Asserted
S1
Delay
>0.25ms
S0
Power Off
S3
Normal
Operation
No Input Clock
Figure 3. Buffer Power-up State Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28400OC | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28400OCT | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28401 | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28401OC | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28401OCT | 100-MHz Differential Buffer for PCI Express and SATA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28400_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Differential Buffer for PCI Express and SATA |
| CY28400-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Differential Buffer for PCI Express and SATA |
| CY28400OC | 功能描述:時鐘緩沖器 100 MHz Diff Buffer PCI Express & SATA RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OCT | 功能描述:時鐘緩沖器 100 MHz Diff Buffer PCI Express & SATA RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OXC | 功能描述:時鐘緩沖器 100 MHz Diff Buffer PCI Express & SATA RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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