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參數(shù)資料
| 型號(hào)： | CY28400 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 100-MHz Differential Buffer for PCI Express and SATA |
| 中文描述： | 100 MHz的差分緩沖器，用于PCI Express和SATA |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大小： | 245K |
| 代理商： | CY28400 |
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CY28400
Document #: 38-07591 Rev. **
Page 2 of 14
Pin Descriptions
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1
.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11011100 (DCh).
Pin
Name
Type
I,DIF
O,DIF
I,SE
Description
2,3
6,7,9,10,19,20,22,23
8,21
SRCT_IN, SRCC_IN
DIFT/C(2:1) & (6:5)
OE_1, OE_6
0.7V differential SRC inputs from the clock synthesizer
0.7V differential clock outputs
3.3V LVTTL active low input for three-stating differential outputs
(DIFT2 and DIFT5 are unaffected by the assertion of OE inputs)
3.3V LVTTL input for selecting PLL bandwidth
3.3V LVTTL input for SRC_STOP#, active low
3.3V LVTTL input for Power Down, active low
SMBus slave clock input
Open collector SMBus data
A precision resistor is attached to this pin to set the differential
output current
3.3V LVTTL input for selecting fan-out or PLL operation
3.3V power supply for PLL
Ground for PLL
Ground for outputs
3.3V power supply for outputs
17
16
15
13
14
26
HIGH_BW#
SRC_STOP#
PWRDWN#
SCLK
SDATA
IREF
I,SE
I,SE
I,SE
I,SE
I/O,OC
I
12
28
27
4,25
1,5,11,18,24
PLL/BYPASS#
VDD_A
VSS_A
VSS
VDD
I
3.3V
GND
3.3V
GND
Table 1. Command Code Definition
Bit
7
Description
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
(6:0)
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
1
2:8
9
10
11:18
Description
Bit
1
2:8
9
10
11:18
Description
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Byte Count from master – 8 bits
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Repeat start
19
19
20
20:27
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28400OC | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28400OCT | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28401 | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28401OC | 100-MHz Differential Buffer for PCI Express and SATA |
| CY28401OCT | 100-MHz Differential Buffer for PCI Express and SATA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28400_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Differential Buffer for PCI Express and SATA |
| CY28400-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Differential Buffer for PCI Express and SATA |
| CY28400OC | 功能描述:時(shí)鐘緩沖器 100 MHz Diff Buffer PCI Express & SATA RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OCT | 功能描述:時(shí)鐘緩沖器 100 MHz Diff Buffer PCI Express & SATA RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28400OXC | 功能描述:時(shí)鐘緩沖器 100 MHz Diff Buffer PCI Express & SATA RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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